SU1195466A1 - Clock frequency synthesizer - Google Patents

Abstract

CLOCK FREQUENCY SYNTHESIZER, comprising, a reference frequency generator, a series-connected frequency divider, a phase detector, a low-pass filter, a tunable generator, the output of which is the output of the device, a second frequency divider, the output of which is connected to another phase input detector, characterized in that, in order to broaden the range of a smooth phase change —H 4 L – O output from the channel in accordance with changes in the phase of the input signal, a series-connected additional phase detector was introduced op, averaging unit, reversible counter, decoder of reversible counter state, and pulse addition and elimination unit and serially connected digital-anap converter and controlled phase shifter, while the output of the reference frequency generator is connected to the appropriate addition and elimination unit of pulses through a controlled phase shifter, the output of which connected to the input of the first frequency divider, the outputs of the bits of the reversible counter are connected to the corresponding inputs of the digital-to-analogue conversion ers, and tunable oscillator output is connected to one input of an additional phase detector, another input of which is the signal input device. Th-4 / I-47FI

Description

The invention relates to communications and can be used in the construction of reference reference generators for nodes and stations of synchronous digital. communication network, as well as in other areas of technology, for example, for measurements in which it is necessary to have a precision oscillation source with a frequency higher than the frequency of the reference oscillator, with the possibility of adjusting the phase of the output signal with discretes smaller than its period.

The purpose of the invention is to expand the range of a smooth change in the phase of the output signal in accordance with changes in the phase of the input signal.

. FIG. Figure 1 shows a structural electrical circuit of a clock synthesizer for a synchronous digital communication network; in fig. 2 and 3 embodiments of the decoder of the sotsoni reversive counter and temporary diaphragms of its work.

The clock synthesizer contains a reference frequency generator 1 ,. controllable phase shifter 2, digital-to-analog converter (D / A converter) 3, unit for adding and excluding pulses SIDII) 4, a decoder of state 5 of a reversible counter, reversible counter 6, first and second frequency dividers (DF) 7 and 8, phase detector 9, lower filter frequency (LPF) 10 averaging unit 11, tunable generator 12 and additional phase detector 13, and the decoder of the state 5 of the reversible counter contains elements AND NOT 14, 15, 16 and 17, elements HE 18, - 18j,, pulse formers 19 and 20 on the positive front and pulse formers 21 and 2 2 on the negative front.

The clock synthesizer works as follows ..

The frequency of the output signal is related to the frequency of the reference frequency generator PQJ, as follows:

Ar vyk ° D op5

where J} ,, 2 division factors, respectively, of the first and second frequency dividers 7 and 8.

In the additional phase detector 13, the phase of the output signal is compared with the phase of the input signal. Pulse Mismatch

depending on the mismatch sign on the first or second inputs of the additional phase detector 13, averaged in the averaging block 11, which is computed as a reversible counter, the capacity of which depends on the time constant of the phase-locked loop (PAL) ,. consisting of the first and second frequency dividers 7 and 8, the phase detector 9, the low pass filter 10 and the tunable generator 12. The longer the time constant of the PLL loop, the greater must be the capacity of the reversible counter.

Depending on the mismatch sign, the averaged error signal in the form of pulses goes to the first or second inputs of the reversible counter 6, and each pulse adds subtracts one from the number written to the reversing counter 6. As a result, the voltage at the DAC 3 output changes by an amount equal to / 2,. where and tso (n voltage swing at the output of the DAC 3, the capacity of the reversible counter 6. The voltage from the DAC 3 output goes to the input of the controlled phase shifter 2, which changes the phase

sinusoidal voltage frequency

0 5 MHz, coming from the output of the reference frequency generator 1 in the range from O to 2ft, in portions equal to 2 0 / 2. Thus, the phase of the sinusoidal signal at the output of the controlled phase shifter 2 depends on the value of the output voltage of the DAC 3. Noticeably a condition occurs when the reversible counter 6 is overfilled or emptied, i.e. switches to either the 11 ... 1 state or the 00 ... 0 state. Suppose, for definiteness, that the reversible counter 6 is in the state 11 ... 1. The next addition pulse at the input of the versatile counter .6 puts it in the state 00 ... 0. This causes a voltage change at the output of the DAC 3

and

by value

and therefore.

SC01

leads to a phase jump of the signal at the 0 output of the controlled phase shifter 2 by 2 and, if no special measures are taken, to a change in the phase of the output signal by

Dg p ..

-7 11.

five.

The decoder of state 5 of the reversible counter serves to form the command for adding a pulse to a sequence of pulses with a tracking frequency of 5 mHz, generated from a sinusoidal signal in the block for adding and excluding pulses 4, when the reversing counter moves from state 00, O to state 11 ,, 1, and to form a command to exclude a pulse from a sequence of pulses with a follow-up frequency of 5 MHz when the reversing counter 6 goes from state 11 ,,, 1 into floor 00 ,,, O, Under this condition, the reverse counter 00 ., O d lzhna match the phase output controlled phase shifter 2 with respect to its input is equal to zero, and the state of the 11, 1, is equal to 21. Due to this, the phase of the signal at the output of the block of addition and elimination of the pulse 4 can be changed indefinitely in the direction of increase, and in the direction of reduction in portions equal. 2i / 2. A change in the phase of the reference signal at the input of a PLL loop causes a transition process of establishing a new phase of the signal at the output of the tunable generator, as a result, the phase of the output signal smoothly changes. The magnitude of this change is D A, -2 if the state of the reversible counter 6 has changed by +1, the transition of the reversing counter 6, the state 11 ,,, 1 causes; O occurrence at the output of the first AND-1 element. with N inputs (Fig. 3a), and the transition to the state 00 .., 0 - the appearance of O at the output of the second element AND-NOT 15 with N inputs (Fig, 3b), the Reversal Counter 6 transition from the state 11 ,. 1 to the 00 ... O state causes the appearance of a pulse at the output of the first pulse shaper 19 to a positive front (Fig. Sv) and a pulse at the output of the second pulse shaper 22 along the negative front (Fig. Ze). These pulses n are derived from a positive signal front (Fig. 3A) and a negative signal front (FIG. 3B), respectively. As a result, at the output of the first (two-input) element AND-NOT 16, a pulse appears (Fig. 3b), which doesn: stupid at the first input of the block for adding and excluding pulses 4 and serves as a command that follows from the sequence of pulses with the following frequency 5 MHz is excluded 66 "one pulse. The transition of the reversible counter 6 from the 00 ... O state to the 1 1 ... 1 state causes the appearance of a pulse at the output of the first pulse shaper 21 along a negative front (Fig. 3g) and a pulse at the output of the second pulse driver 20 on the positive front (phi .Zd). These pulses are obtained from the negative signal front (Fig. 3A) and the positive signal front (Fig. 3B), respectively. As a result, a pulse appears at the output of the second (two-input) element IS-HE 17 (Fig. 3i), which enters the input of the addition and elimination unit of pulses 4 and serves as a command that adds to the sequence of pulses with a following frequency of 5 MHz one pulse. The transition of the reversible counter 6 from the state 11 ... 1 (00 ... 0) to any other than the state 00 ... O (11 ... 1), and vice versa, causes the appearance of pulses at the output. one of the pulse formers 19, 20, 21 and 22, but on the outputs of the (two-input) elements AND-NOT 16 and 17 of the exclusion and addition commands are not. will be. The use of this invention makes it easy to synchronize even high-speed digital transmission systems according to the requirements of the GITC. For example, the quaternary transmission system has a clock frequency of 139.264 kHz, the division factors of the first and second DF 7 and 8 in this case are 625 and 17408, respectively. The size of the D / A converter 3 can be chosen as N 8. Consequently, one adjustment step is equal to the phase shift of the oscillator of the reference frequency 1 on the ACM 200 40 0, G810 2 256 T A p is the oscillation period of the reference frequency generator 1. This causes the same phase shift of the output oscillation tunable generator 12. The phase shift on It 0.78-10s is it oreo-oIT- ..-. ° 0.109, where T & C is the oscillation period of the tunable generator, i.e. adjustment step less than 1/9 of the output

51195466

hesitation. Naturally, using the trimming step will be even smaller, the DAC 3 will be N 8 dp lower speed, which allows you to choose a smaller transmission system (tertiary p, etc.), as well as DAC 3.

Claims (1)

A TACT FREQUENCY SYNTHESIS device, comprising, a reference frequency generator, a first frequency divider, a phase detector, a low-pass filter, a tunable generator, the output of which is the output of the device, and a second frequency divider, the output of which is connected to another input of the phase detector, which differs for the purpose expansion of a smooth phase change a whose input is the signal input of the device. In addition, the output signal • • range is in accordance with changes in the phase of the input signal, an additional phase detector, an averaging unit, a reversible counter, a decoder for reversing counter status and a pulse adding and eliminating unit, and a digital-to-analog converter and a controlled phase shifter are connected in series, the output of the reference frequency generator through a controlled phase shifter is connected to the corresponding input of the block adding and eliminating pulses, the output to which is connected to the input of the first frequency divider, the outputs of the digits of the reversible counter are connected to the corresponding inputs of the digital-analog converter, and the output of the tunable generator is connected to one of the inputs of the additional phase detector, the other