SU915240A1 - Frequency synthesizer - Google Patents

Description

The invention relates to radio engineering and can be used in receiving and transmitting and control and measuring devices.

¹ Known frequency synthesizer containing connected in a ring controlled oscillator, mixer, frequency divider with variable division factor, phase detector and low pass filter, connected in series reference oscillator and harmonic generator, the output of which is connected to another input of the mixer, as well as a digital comparator and in series connected counter and digital-analog converter, the output of which is connected to another control input of the controlled generator, while another output of the reference generator is nen to the input of the frequency divider with a fixed division factor, the output of which is connected to another input of the phase detector and the first input of the digital comparator, a second input coupled to an output of the frequency divider with a variable division factor [1].

However, in a known device, auto-tuning is disabled when operating in a wide frequency range.

2

The purpose of the invention is to increase reliability when operating in the frequency range.

This goal is achieved by the fact that in the frequency synthesizer, containing connected in a ring controlled oscillator, mixer, frequency divider with a variable coefficient

10 divisions, a phase detector and a low-pass filter, a series-connected reference oscillator and a harmonic generator, the output of which is connected to another mixer input, as well as a digital comparator and sequentially connected counter and digital analog converter, the output of which is connected to another control input of the controlled oscillator , while the other output of the reference generator is connected to the input of a frequency divider with a fixed division factor, the output of which is connected to another input of the phase detector and digital input

25 of the comparator, the second input of which is connected to the output of a frequency divider with a variable division factor, entered in series D-trcgger, the first AND-NOT element and

30 (the second element NAND, the output of which

3

915240

four

connected to the counter input, with This the output of a frequency divider with a fixed division factor is connected to the C input of the D-flip-flop and another input of the first NAND element, the output of the digital comparator is NOT connected to the other input of the second element AND, the trigger is connected to the output of a frequency divider with a variable division factor, while the input of the D-flip-flop is the input of a logical unit.

Figure 1 shows the structural electrical circuit of the device; figure 2 - diagrams explaining his work. .

The device contains a controlled oscillator 1, a divider 2 frequencies with a variable division factor (DPKD), a generator of harmonics, a reference oscillator 4, a mixer 5, a phase detector 6, a divider 7 of a frequency 'O' with a fixed division factor (DFCD), 8 low-pass filter (LPF), as well as D-flip-flop 9, digital comparator (CK) 10, element EE 11, counter 12, digital-to-analog 25 converter (D / A) 13, element EE 14, forming an auto search block 15.

The frequency synthesizer works as follows. thirty

In synchronization mode, the inputs of the digital comparator 10 receive reference pulses from the output of the DFCD 7 (Fig. 2a) and pulses from the output of the PDKD 2 (Fig.26) so that they alternate during the time35. In this case, the output of the digital comparator 10 (figv) does not have differential pulses, but the level of the logical • • · ’is maintained. At the same time the output of the D-flip-flop 9 (Fig.2G) saved. The logic level ”0 *’, since its K-input comes from the DPKD 2 output, is basically the logic level ”1” (with the exception of short negative pulses).

The logical level "0" ¹ from the output of the D-flip-flop 9 is fed to the second input of the element AND-NO 14, the output of which forms the level of the logical "* 1" (fig.2d), allowing passage through the AND-NOT element The signal 11 output from the catch ⁵⁰ of the digital comparator 10 the input counter 12. The mode matching at the output of aND-nO element 11 is stored a logic "0" (2e) code counter 12 is not "5 varies and the output DAC 13 The second input of the controlled generator 1 receives a constantly controlling voltage.

When synchronization in the phase-locked loop of the phase-locked loop (f £ e ps) is connected with switching from one frequency to another or for another reason, at the output of the digital comparator 10 (FIG. 2b) 65 are formed.

differential frequency pulses that through the element AND NOT 11 (FIG. 2e) are fed to the input of the counter 12 and change its state. In accordance with the changing counter code 12 _, a step voltage is formed at the output of the D / A converter 13, which acts on the second control input of the controlled oscillator 1 so that the resulting error in frequency is reduced. . i: When switching from one frequency

'to another in a wide-range input frequency synthesizer DPKD 2 with mixer 5 may enter the intermediate frequency £ _PCs, several times greater .nominalnoy ^ pchnomin. r which is usually formed in synchronism mode. This will happen when switching from the upper frequency of the controlled oscillator 1 to the lower one. Then so -ϊποΑετ-п £ пц,

where £ is the frequency from the output of the controlled oscillator 1; £ to ^ st ~ frequency of the stand from the generator output 3 harmonics.

If DPKD 2 is designed for a nominal operating frequency, then with a higher input frequency, its normal operation stops, i.e. at its output there will be no pulses, but one of two possible states of logical ¹ Ό ^{1 1} or logical '1 ¹ ’is set. If a logical 'Ί ¹ * is set at the DPKD 2 output, then the digital comparator 10 does not stop working and reference pulses pass to the output of its 35 (i.e., FIG. An auto search is performed. If logical ¹ '0''is set at the DPKD 2 output, then the digital' Ί ”is set at the output of the digital comparator 10. The logical · Ό ' ¹ input from the DPKD 2 output to the ί input of D-flip-flop 9 does not set the D-flip-flop to the state of logical' * 0 * 'at its output. Therefore, the first impulse coming from DFCD 7 to the c-input of D-flip-flop 9 sets it to the logical state '' 1 ''.

This logical ¹ '1' ¹ permits the passage of reference pulses with DFCD 7 __ through the second element AND-NOT 14 to 5 "the input of the first element AND-NOT 11. And since the first input of the element AND-NOT 11 is set to a logical level ¹ * 1 · ', then the reference pulses pass through the element AND-NOT 11 to 55 the input of the counter 12. Thus, an auto search is performed.

The use of the proposed device makes it possible to exclude the possibility of opening the auto-support ring when it is operating over a wide frequency range (self-locking) and when using PDCD calculated for the nominal input frequency. This will allow you to create on 65 durable economical on consumed

915240

6

Power frequency synthesizers that can be used in devices with a limited resource supply sources.

Claims (1)

Claim A frequency synthesizer that contains a looped controlled oscillator, a mixer, a variable divider frequency divider, a phase detector and a low pass filter, a serially connected reference oscillator and a harmonic generator, the output of which is connected to another mixer input, as well as a digital comparator and a serially connected counter and digital analog converter, the output of which is connected to another control input of the controlled generator, while the output of the reference generator is connected to the input of cases frequency of Tell with a fixed division factor, the output of which is connected to the other input phase detector and the first input of a digital comparator, the second input of which is connected to the output of a frequency divider with a variable division factor, which is different in that with the aim of increasing. reliability when working in a range frequencies, are entered. sequentially connected D-flip-flop, the first element AND-NOT and the second element NAND, the output of which is connected to the counter input, and the output of the frequency divider with a fixed division factor is connected to the C input of the D-flip-flop and another input of the first element NAND, to another input of the second 15 of the NAND element is connected to the output of a digital comparator, the input E of the D-flip-flop is connected to the output of a frequency divider with a variable division factor, while the input of the D-flip-flop is 20 is the input of a logical unit.