SU1149406A1 - Pulsed phase-shifting device - Google Patents

Abstract

A PULSE PHASE-SHIFTING DEVICE containing a series-connected phase detector, the first input of which is the device input, a low-pass filter, a controlled pulse generator and a synchronous counter, as well as a phase shift code adjuster, characterized in that, in order to improve noise immunity, the outputs of the synchronous counter and the setter of the phase shift code are connected to a binary adder, the output of which, corresponding to the upper section of the synchronous counter, is connected to the second input of the phase de the highest bit of the synchronous counter is the output of the device.

Description

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The invention relates to radio engineering and can be used in radio measuring devices.

A pulsed phase-shifting device is known, comprising a ring-connected phase detector, a low-pass filter, a controlled pulse generator and a synchronous pulse counter, as well as two comparison units, a setting for the phase shift code and trigger 1. However, the known device is complicated.

Closest to the invention, the technical essence is a pulsed phase-shifting device comprising a phase-connected phase detector, the first input of which is the device input, a low-pass filter, a controlled pulse generator and a synchronous counter, as well as a setting for the phase shift code 2.

However, the known device has insufficient noise immunity, which manifests itself in the displacement of the fronts of the output voltage due to disturbing signals, mainly due to the spread of the propagation delay time of the signals in the synchronous counter elements and the difference in the electrical lengths of its output circuits, which leads to the appearance of interfering short pulses in subsequent circuits and, as a consequence, to the displacement of the fronts of the output voltage.

The purpose of the invention is to improve noise immunity.

This goal is achieved by the fact that in a pulsed phase shifter containing a phase-connected phase detector, the first input of which is the device input, a low-pass filter, a controlled pulse generator and a synchronous counter, and set the 4V K phase shift code to the synchronous outputs the counter and setter of the phase shift code is connected to a binary adder, the output of which, corresponding to the first digit of the synchronous counter, is connected to the second input of the phase detector, while the master the bit of the synchronous counter is the output of the device.

FIG. Figure 1 shows a structural electrical circuit for a pulsed phase shifter; in fig. Figures 2 and 3 show voltage plots at various points in a pulsed phase shifter for different phase shifts given by the potentials of the control code of the setpoint for the phase shift code at the inputs of the binary adder.

The pulsed phase-shifting device contains a phase detector 1, a low-pass filter 2, a controlled pulse generator 3, a synchronous counter 4, a phase shift code setter 5, and a binary adder 6.

Pulsed phase-shifting device operates as follows.

The input signal of the device (Fig. 2a and Fig. 3a), having the form of a meander FO frequency, is fed to the first input of the phase detector 1, to the second input of which impulse voltage is output from the output of the k-th bit of the binary adder b formed as follows. In the steady state, the frequency of the pulses of a controlled generator of 3 pulses is equal to

,

where k is the size of the synchronous counter 4, as well as the setting device 5 of the phase shift code and the size of the binary adder 6.

Therefore, at the output of the synchronous counter 4, to the input of which pulses are received from the controlled pulse generator 3, a varying binary code with a repetition frequency FO is formed (Fig. 2a, b, c and Fig. Za, b, c). In particular, at the output of the senior discharge of the synchronous counter 4, and, consequently, at the output of the device, meander voltage P. also takes place (Fig. 2 in and Fig. 3 in).

The sequence of codes from the outputs of the bits of the synchronous counter 4 (FIG. 2 a, b, c, and figs. Over, b, c) goes to the first inputs of the binary adder 6, to the second inputs of which the control code is supplied from the setting unit 5 of the phase shift code (Fig. 2e, e, g and Fig. Zd, e, g). If the phase shift code is zero, then the outputs of the binary adder 6 have the same code combinations as the outputs of the synchronous counter 4. In particular, in the k-th output

The discharge of the binary adder 6 is the same meander of the frequency f as in the kth discharge of the synchronous counter.

Suppose that a phase detector with a discriminating characteristic is selected to ensure that the phase-controlled frequency control system of the controlled oscillator has 3 pulses in synchronous mode with zero phase detuning of the input signals of phase detector 1. Then with zero code in unit 5 of the phase shift code, the output signal of the device taken from The k-th bit of the synchronous counter 4 is in phase with the signal at the input of the device.

With an arbitrary nonzero code of the setting device 5, the phase shift code (Fig. 2 d, e, g, Fig. 3, g) is the result of the addition of this code with the current code sequence of the synchronous counter 4 (Fig. 2a, b, c, fig. Za, b , c,) in the rd bits of the binary adder 6, still has the frequency of Re, but does not coincide with the current code at the outputs of the synchronous

counter 4, and it is ahead of time in so many pulse periods of the controlled generator of 3 pulses, how much the setpoint code 5 of the phase shift code differs from zero, i.e., the value of this code (Fig. 2,3, and, k, Fig. 3 3, and, k). Accordingly, at the output of the k-th bit of the binary adder, b is the meander of frequency F, (Fig. 2k, Fig. Qc), time-shifted relative to the voltage in the k-th bit of the synchronous counter 4 (Fig. 2c, Fig. Sv) . Since the phase locked loop system maintains the equality of the phases of the input signal of the device (Fig. 2, d, Fig. Dg) and the output signal of the k-th bit of the binary adder 6 (Fig. 2k, Fig. W), the phase the shift between the input signal and the output signal of the device, taken from the k-th output of the synchronous counter 4.

In the proposed device, the delay spread of the pulse fronts at the outputs of the binary counter, as well as the final switching time of the elements of the binary adder, do not lead to malfunctions in the operation of the other elements and thus provides increased noise immunity of the proposed phase shifter.

Claims (1)

A PULSE PHASE-MOVING DEVICE containing a phase detector connected in series, the first input of which is a device input, a low-pass filter, a controlled pulse generator and a synchronous counter, as well as a phase shift code adjuster, characterized in that, in order to increase noise immunity, to the discharge outputs of the synchronous counter and a phase shift code setter, a binary adder is connected, the output of which, corresponding to the highest section of the synchronous counter, is connected to the second input of the phase detector while the high-order bit of the synchronous counter is the output of the device. 90WII HS Fig-1