SU1127097A1 - Frequency w divider with variable countdown - Google Patents

Abstract

FREQUENCY DIVIDER WITH A VARIABLE DIVISION COEFFICIENT, containing the first and second frequency e dividers, the counting inputs of which are connected to the reference frequency bus, the first and second control code generation counters, the output bits of which are connected to the inputs of the division factor setting of the corresponding controlled frequency dividers inputs. settings of the initial values of the control code - with the installation bus. the output bus is connected to the output of the first controlled frequency divider, characterized in that, in order to expand the functionality by providing a linear-step change in the output frequency as a function of time, two frequency dividers with constant division factors are introduced, the first of which connected to the output of the first controlled frequency divider, the output to the counting input of the second counter of the formation of the control code; the input of the second frequency divider with a constant division factor equal to twice the value of the division factor of the first (L frequency divider with a constant division factor, is connected to the output of the second controlled frequency divider, and the output is connected to the counting input of the first counter of the control code generation. NP with

Description

The invention relates to a pulse technique and can be used in automation and electric drive devices. A tunable frequency divider is known, which contains a signal generator, a binary counter, a buffer and information registers, an adder, two AND elements, an inverter, two comparison elements, a trigger, and OR and I-ШШ ij. The disadvantage of this device is that it does not need to form an output frequency that changes as a function of time. The closest in technical essence to the present invention is a device containing the first and second controlled frequency elements, the counting inputs of which are connected to the reference frequency bus, the first and second control code generation counters j whose discharge outputs are connected to the inputs of the division factor 1 controlled frequency dividers, the installation inputs of the initial value of the control code of which are connected to the installation bus, the output of the first controlled frequency divider is connected to the output bus and About the counting input of the second control code generation counter, the counting input of the first control code generation counter is connected to the output of the second controlled frequency divider, the output bus connects to the counting input of the counter of the allowable integration zone, the output of which is connected to the switch input, and the reset input is connected to the installation bus 2 The disadvantage of this device is the nonlinear nature of the change in the output frequency as a function of time, since with each output pulse the frequency changes with a constant rate: g & i. The purpose of the invention is to enhance the functionality by providing a linear-step change in the output frequency as a function of time. The goal is achieved by the fact that in a frequency divider with a variable division factor, containing the first and second controlled frequency dividers, the counting inputs of which are connected to the frequency reference bus, the first and second counters of the control code for the world, the outputs of the bits of which are connected with the inputs of the installation of the division factor of the corresponding controlled frequency dividers, the inputs of the installation of the initial values of the control code - with the installation bus, the output bus is connected to the output of the first controlled frequency divider, Two frequency dividers with constant division factors, the input of the first of which is connected to the output of the first controlled frequency splitter, are output. Output - With the counting input of the second counter of the control code generation, the input of the second frequency splitter with a constant division factor equal to twice the division factor of the first divider. frequency with a constant division factor, is connected to the output of the second controlled frequency divider and the output is connected to the counting input of the first counter of the formation of the control code. The drawing shows a structure of a frequency divider circuit with a variable division factor. The device contains the first and second controlled dividers 1 and 2 frequencies, the counting inputs of which are connected to the reference frequency bus 3, the first and second counters 4 and 5 of the control code generation, the bit outputs of which are connected to the inputs of the division factor setting of the corresponding controlled frequency dividers The inputs for setting the initial values of the control code are connected to the bus 6 of the installation, and the output bus 7 is connected to the output of the first controlled frequency divider 1, two dividers 8 and 9 frequencies with a constant power factor, the input of the first 8 of which are connected to the output of the first controlled splitter 1 frequency, the output with the counting input of the second counter 5 generating the control code, the input of the second splitter 9 frequency with a constant division factor is connected to the output of the second controlled splitter 2 frequency, the output with the counting input the first counter 4 forming the control code. The division factor of divider 9 is twice the division factor of divider 8. The device operates as follows.

3

in the initial state in the meters

A and 5, the signal on bus 6 records control codes defining the initial division coefficients and dcc divisors 1 and 2, respectively.

When the reference frequency Pd arrives on the bus 3 at the outputs of dividers 1 and 2, pulses are generated with frequencies determined by the corresponding initial values of the division factors of the said dividers. These pulses arrive at the inputs of dividers 8 and 9, respectively, from the outputs of which the pulses arrive at the Counting inputs of counters 5 and 4, while counter 5 operates in the forward count mode, counter 4 in the countdown mode.

With each pulse of the input frequency at the counting inputs of counters 5 and A, the control codes 1: neither at the outputs of the discharge chips change by one. Corresponding to the change in the control codes of the counters 5 and 4, the division factors of the dividers 2 and 1, i.e. the division ratio of divider 1 decreases, and the division ratio of divider 2 increases, which leads to a change in the frequency of the pulses in the outputs of the controlled frequency dividers 2 and 1, the latter being linearly decreasing.

Indeed, to ensure that the output frequency of the divider 1 varies linearly

W)

where ff) is the initial output value

frequency - the output frequency increment

per unit time, the current time, the division factor Nj of the divider 1 must be changed according to the hyperbolic pattern

 piece1;

where FQ is the reference frequency.

Taking into account the small values of the relative frequency output frequency at large values of the division factor and the change of the control code discretely with a step equal to one, with sufficient accuracy for practice accuracy, you can use the recording form for continuous functions.

When changing the output frequency d linearly coefficient

270974

division of divider 2, defined by

control code of the counter 5 forming the control code, the counting input of which receives pulses

ui-t + f and

ic (i.

where K with frequency

division factor of divider 8, determined by the extrusion

t i {- l 2iHt + 2NiH.K

10 fJsW M H Iis Wi-- --1

about : .

where the initial value of the divider coefficient 2, the output frequency of the divider 2 is defined by the expression:

fo2K

. 2 (M-,

Mg () N 42 ts1 + 2M2n1 At the counting input of the counter 4 postU;

1gSH

I

drip pulses with a frequency of 11

f - - | - -I 7

9 to

whereby the division factor of divider 1 is changed according to

  I. .

N W - NiH-lf4lt) dl

d

-dt,

J ln 2 „142М2, .К,

 - the initial value of the coefficient of division of the divider 1.

Define the integral F "

3l.

J

t lt 2fH-t + 2H2Hl

for which we denote ui 01, 21 b, 2kln K C. Then the last phase. can be written as t p

 | a-bcc This integral has a different value depending on the value of ac-b. However, with 7 O and U. O expressions for integral 3 have no physical meaning, with b O, i.e. the last expression after the transformation takes the form

fo “,,

ssh

Zl

55 where A is a constant that is FROM the initial conditions at t 0 and is equal to. Then the expression for N, (t) will be ..

511270976

fr. The introduction to the device of two delN (t) "r -77-t frequency gates with constant coefficients of + 4, division divisions, has made it possible to achieve

which coincides with the first expression of the 5 linear-step change of clock dp N (i). Consequently, the BI device for following the output pulses, provides for a change in the output, which expanded the functional possible frequencies in a linear-stepwise manner and the area of use of the law as a function of time. roystva

(under certain initial conditions)

Claims (1)

A FREQUENCY DIVIDER WITH A VARIABLE DIVISION FACTOR, containing the first and second controlled frequency dividers, the counting inputs of which are connected to the reference frequency bus, the first and second control code generation counters, the discharge outputs of which are connected to the division coefficient setting inputs of the corresponding controlled frequency dividers, initial value setting inputs control code - with the installation bus, the output bus is connected to the output of the first controlled frequency divider, characterized in that, in order to expand the function of possibilities by providing a linear-step change in the output frequency as a function of time, two frequency dividers with constant division factors are introduced into it, the input of the first of which is connected to the output of the first controlled frequency divider, the output is with the counting input of the second counter for generating the control code, the input of the second a frequency divider with a constant division coefficient equal to twice the value of the division coefficient of the first frequency divider with a constant division coefficient, connected to the output of the second managed frequency divider, and an output - with a counting input of the first counter forming the control code. > are you25