SU1124424A1 - Pulse frequency-phase discriminator - Google Patents

Abstract

PULSE FREQUENCY-PHASE DETECTOR containing the first, second, third and fourth D-triggers, two delay blocks, the inputs of each of the Topi are connected respectively to the synchronization inputs of the first and second 3) triggers, two elements SH and integrator, the output of which is the output pulse frequency-phase detector, the inverse outputs of the first and second. D flip-flops are connected respectively to D-inputs of the second and first 3) -triggers, and the synchronization inputs of the first and second 3) -triggers are connected to the input sources and connected respectively to the R-inputs of the second and first D-triggers, differing in that In order to simplify, the inputs of the integrator are connected to the outputs of the SHS elements, the first inputs of which are connected respectively to the direct outputs of the third and fourth D triggers, and the second inputs are connected respectively to the third and fourth D triggers, 9 vrhd syn. the synchronization of which is connected respectively to the outputs of the first and second delay blocks, while the direct output of the first D-trigger is connected by a cD-input of the third D trigger, and the direct output of the second D-trigger is connected to the p-input of the fourth D-trigger.

Description

The invention relates to radio engineering and can be used in fast acting phase-locked loops with a low level of frequencies that are multiples of the tracking frequency. A pulse-frequency detector is known, containing two 3 flip-flops and an integrator, the inputs of which are connected respectively to the direct output of the first D-trigger and the inverted output of the second 33-trigger, and the synchronization inputs of each of D are the trigger is with the device inputs and is connected respectively to the input of the zeroing of another B-trigger, the inverse output of the first D-trigger is connected to the information D-input of the second D-trigger, and the inverse input of the second D-trigger with info matsionnym- first -Log D) D1 trigger pulse However, the known frequency-phase detector has a low speed, due to the pulse frequency adjustment and phase at any phase shift between the reference and the adjustable frequencies. The closest technical solution to the proposed is a pulsed frequency-phase detector containing the first, second, third and fourth D-triggers, two delay blocks, the inputs of each of which are connected respectively to the synchronization inputs of the first and second 1) triggers, two elements OR and an integrator, the output of which is the output of a pulse frequency-phase detector, the inverse outputs of the first and second D-triggers being connected to the D-inputs of the second and first D-triggers, respectively, and the synchronization inputs of the first Go and second D triggers are connected to input sources and are connected respectively to the R inputs of the second and first D triggers, the third and fourth D triggers are included in two additional processing channels connected between the OR elements and the integrator inputs However, the lime pulse frequency-phase detector has a rather complicated scheme. The purpose of the invention is to simplify the pulse frequency-phase detector. The goal is achieved by the fact that the pulse frequency-phase detector containing the first, second, third and fourth D triggers, two delay blocks, the inputs of each of which are connected respectively to the synchronization inputs of the first and The second D-triggers, two OR elements and an integrator, the output of which is the output of a pulse frequency-phase detector, the inverse outputs of the first and second D triggers are connected respectively to the D-inputs of the second and n The D triggers, and the synchronization inputs of the first and second O triggers are connected to the input sources and connected respectively to the R inputs of the second and first D triggers, the integrator inputs are connected to the outputs of the OR elements, the first inputs of which are connected respectively to the direct three outputs, the second and fourth D triggers, and the second inputs are connected respectively to the D inputs of the third and fourth L triggers, whose synchronization inputs are connected to the outputs of the first and second delay blocks, respectively; My output of the first D trigger is connected to the JD input of the third D trigger, and the forward output of the second D trigger is connected to the U input of the fourth g-trigger. Figure 1 shows the structural electrical circuit of the proposed pulse frequency-phase detector; Fig. 2 illustrates stress plots showing its operation. Pulse frequency-phase detector contains the first-fourth triggers. 1-4, two blocks 5 and 6 of the delay, two elements IL 7 and 8, integrator 9, sources 10 and 11 of the input signals. Pulse frequency-phase detector works as follows. From the source 10 comes, for example, the frequency PI (Fig.2A), from the source 1 1 - the frequency FQ (Fig.26). In the initial state, the outputs of the J-triggers 1-4 and the outputs of the elements OR 7 and 8 present a logical zero voltage. Let the PI frequency be ahead of the frequency PO in phase; then the front of the first frequency pulse G, D trigger 1 switches to the state

.3

logical unit, and at the output of the element OR 7, the level of the logical unit also appears, and if the phase difference between F and

j - 2i, where L is the delay time in block 5 of the delay, and T is the period of the reference frequency, then D-trigger 3 also switches to the state of the logical unit, in which it remains until those nopj while the difference between the phases and the FQ is greater than - .2ii. In this case, the output

TO. ,

element 1 7 7 is also present

logical unit voltage while / j / j

 (figv). Come-2m

o.To

The frequency f-squares switch to one state only D trigger 1, and the frequency pulses to zero state, with 33 trigger 3 remaining in the zero state, and pulses appear at the output of the OR element 7, the duration of which is proportional to the phase difference: frequencies F, and FQ .. Moreover, while the frequency FI FQ, or when the phase F of the frequency is F, F, the input of the element OR 8 maintains a logical zero level, since the B-triggers 2 and 4 are in the logical zero state. The voltage at the output of the element OR 7 is integrated into the integrator 9 (Fig. 2d, the voltage at the output of the integrator 9 increases until a common-mode mode occurs, while the outputs of the elements OR 7 and 8 present a logical zero. These signals keep the integrator 9 in the closed state, at which the output voltage remains constant and there is no voltage ripple.

Now let the frequency F, (fig.2d) be out of phase with the frequency Fg (fig.2e), then with the front of the first pulse of the frequency FQ D-trigger 2 switches to the state of the logical unit, and at the output of the U1I element 8

. is also the level of the logical unit, and if the phase difference

2442Л4

 FI and fj, more than 1 C I ToDI TD I

trigger 4 also switches to the logical one, where it is until pas1 i

phase tolerance between F and F is greater

At the output of the element OR 8, the voltage of the logical unit is also present (Fig. 2g). When lsr} - -2 «1 t-Q pulse frequency switches. in the single state only the D-trigger 5 2, and the frequency pulses F in the zero state, while D-Trigger

I

4 remains in the zero state, and at the output of the element OR I there appear pulses, the duration of which

0 is proportional to the phase difference

frequencies f, and fo. Moreover, while F, Fjj, or when the phase of the frequency FO is ahead at F PO-, the output of the SHSh 7 element is maintained at the logical zero level, since the D triggers 1 and 3 are in the logical zero state. The voltage at the output of the element OR 8 is fed to another input of the integrator 9, while the voltage at the output of the integrator 9 decreases (Figure 2h) until the common-mode mode occurs.

Compared with the base object, the proposed pulse-frequency-phase detector has a higher speed, since the output of one of the OR elements, depending on the sign of the frequency difference or phase, maintains a logic level.

units all the time, noKafitf - 2.1, - -.

and the output voltage is faster reaching the level at which the synchronization mode appears. As a result of a significant simplification of the circuit, the pre-launch and sweet frequency-phase detector, compared with the prototype with ojE iHaKOBOM, has a quick lower cost.

Claims (1)

457) PULSE FREQUENCY-PHASE DETECTOR, containing the first, second, third and fourth D-triggers, two delay blocks, the inputs of each of which are connected respectively to the synchronization inputs of the first and second S-triggers, two OR elements and an integrator, the output of which is the output of the pulse frequency-phase detector, with inverse outputs ^; first and second. D-flip-flops are connected respectively to D-inputs of the second and first P-flip-flops, and the synchronization inputs of the first and second B-flip-flops are connected to input sources and connected to the R-inputs of the second and first P-flip-flops, respectively, which differs in that in order to _simplify} integrator inputs coupled to the outputs of OR elements, first inputs of which are connected respectively to the direct outputs of the third and fourth P -triggerov and second inputs connected respectively to the third 17 and fourth -Log D -triggerov inputs synchro tion S which are connected respectively to the outputs of the first and second delay units, wherein the direct output of the first P -triggera connected cD O -Log third flip-flop and the direct output of the second D · flip-flop is connected to the fourth P p -Log -triggera.