SU985929A1 - Pulse frequency-phase detector - Google Patents

Description

(54) PULSE FREQUENCY-PHASE DETECTOR.

The invention of mercury technology has been developed and can be used in various types of radio engineering devices, in particular, in phase-locked loop devices. .

(Known pulse frequency-phasebbtil detector (ICFD), containing) first and second triggers, each of which has a trigger input, triggered on a leading edge, an output and a reset input. Alkhods of the first and second pulse formers are connected, respectively, to the trigger inputs of the first and second triggers, with one of the inputs of the first and second coincidence circuits. The output of each trigger is connected to one of the inputs of each matching circuit, as well as the corresponding integrator input, while the output of each matching circuit is connected to the reset input of that trigger whose trigger input is connected to one of the inputs of the matching circuit C13.

Closest to the present invention is a pulsed frequency-phase detector containing two o-flip-flops and an integrator, the inputs of which are connected respectively to the direct output of the first D-flip-flop and the inverse output of the second D-flip-flop, the synchronization inputs of each O-flip-flop are the inputs of the device and are connected respectively to the input of the set to zero; another D-flip-flop, and the D-inputs of each o-flip-flop are supplied with a logic level.

10 unit C2.

However, the known pulse frequency-phase detectors have a significant level of pulse noise in the output signal.

15

The purpose of the invention is to reduce the level of impulse noise in the output signal.

To achieve the goal in a frequency-phase detector, containing two

20 D-flip-flops and an integrator, the inputs of which are connected respectively to the direct output of the first D-flip-flop and the inverse output of the second O-flip-flop, and the output is the output of the device, and the synchronization inputs of each D-flip-flop are device inputs and are connected respectively with the input of the setting to zero of another O-trigger, inverse output

30 of the first O-flip-flop is connected to the informational D-input of the second 0-flip-flop, and the inverse output of the second D-flip-flop is connected to the information D-input of the first D-flip-flop.

Fig; 1 shows the structural electrical circuit of the proposed 5 devices; in fig. Figures 2 and 3 show voltage plots showing the operation of the device.

The device contains the first and second O-triggers 1 and 2, the integrator 3. 10

The device works as follows.

In the initial state at the outputs of the D-flip-flops 1 and 2, the voltage levels correspond to a logical zero, and 15 at the inverse outputs, the voltage levels correspond to a logical one. The first pulse supplied to the start input of the first O-trigger and the reset input of the second O-flip-flop 2, 20 sets the output of the first O-flip-flop 1 voltage corresponding to the level of the logical unit, since the information input of this O-flip-flop is connected to the inverse output 25 of the second D-flip-flop 2 and does not change the logical state of the second o-flip-flop 2. The second pulse, supplied to the start input of the second D-flip-flop 2 and to the reset input of the first D-flip-flop 1, returns the first D-flip-flop 1 to the initial logical state and does not change the logical The second state of the second D-flip-flop 2, since at the moment of arrival of the second pulse at the information input of the second o-flip-flop 2, connected to the inverse output of the first D-flip-flop 1, was a logic zero level. The output of the first p-flip-flop 1 is connected to the first input Ig (+) of integrator 3, the output of the second O.-flip-flop -2 is connected to the input Ilgx () of integrator 3. From the output of the first D-flip-flop 1 a positive pulse is removed, equal to the phase difference of the first and second pulses. 45 FIG. Figure 2 shows the stress plots for this case.

FIG. Figure 3 shows the voltage plots where the second pulse is ahead of the first pulse in phase. In this case, 50 the logical state of the first D flip-flop 1 does not change, and

the output of the second O-flip-flop 2 occurs a positive pulse equal to the phase difference of the first and second pulses. At the output of the integrator 3, a voltage decrease is proportional to the pulse width of the phase difference from the second O-flip-flop 2. The minimum pulse duration at the flip-flop outputs can be no more than the trigger trigger delay time. The introduction of new connections allows in the steady state (at zero phase shift between the input signals), at the direct output of the O-flip-flop 1, get a logical O, and at the inverse output of the other O-flip-flop 2 - a logical one. These signals keep integrator 3 in the closed state. The output voltage remains constant and there is no voltage ripple.

; Thus, in the proposed device, compared with the prototype, the level of impulse noise is significantly reduced.

Claims (2)

1. Patent SShL 4105947, cl. 331-1A, 1978. 2. German Patent No. 2912406, cl. H 03 V 3/04, 1980 (prototype). Isn ( Shchk. Rig g % one I Ue.