SU1332554A2 - Clock pulse generator synchronization device - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to increase the synchronization accuracy. The device contains n synchronization channels, as well as an adder 6, comparators 7 and 8, zl-OR 9, shaper 10 reset pulses, low-pass filter 11, threshold unit 12, controlled by r-13, frequency divider 14 and reference Hr 15. Phase Difference Signals with High /. the strokes n of the synchronization channels are summed with the reference voltage of Mr. 15, and the result is compared in Comparators 7 and 8 with voltages corresponding to the maximum and minimum values of the phase difference. The signals developed by comparators 7 and 8 are combined by the OR 9 element and are fed to the shaper 10, a powerful reset pulse for divider 14 and a frequency divider in each of the n channels. They are reset to a state in which the operating point of the synchronization device returns to the middle of the control x-ti and at the same time excludes the possibility of its jumping to another period and so on. the false adjustment of Mr. 13 is eliminated. The goal is achieved by the introduction of comparators 7 and 8, Element OR 9 and the former 10. 2 Il. (L fi T y 18 U 00 00 with ISD ate 4 N) FIG. 2

Description

one

FIELD: engineering.

integrated communications networks, can be used in time-multiplexed transmission systems for synchronizing clocks, and is an improvement to the device by author. No. 696620.

The aim of the invention is to improve the synchronization accuracy.

Figures 1 and 2 show the structural electrical circuit of the devices.

The clock synchronization device contains n channels (where, 2, ...), each of which contains control block 1, input key 2, first frequency divider 3, phase discriminator 4, amplifier 5, as well as adder 6, first 7 and second 8 comparators, element OR 9, shaper 10 pulse resets, fnlpp 11 low frequencies (LPF), threshold unit 12, controlled oscillator 13, second frequency divider 14, reference oscillator 15.

The synchronization device operates as follows.

The first input of the input keys 2 is supplied with a clock frequency signal, which is extracted from the incoming pulse streams. These clocks are also applied to one of the input control units 1. To the other input of the input keys 2, a control signal is supplied from one of the outputs of the blocks 1, through the other inputs of which the signals of the initial installation of the first dividers 3 are supplied.

After installing the first dividers 3, the clock signals from the outputs of the input keys 2 come to their inputs. After the dividers 3, the signals are sent to the first inputs of phase discriminators 4, to the other inputs of which the signal of the second divider 14 arrives. Phase discriminators 4 give phase difference signals between the clock oscillations of the controlled oscillator 13 and oscillations of the selected clock signals. These signals are amplified in amplifiers 5, summed in adder 6, and fed to a low-pass filter 11 and the first 7 and second 8 comparators.

The input voltage of the reference oscillator 15 is also supplied to the input of the adder 6. From the outputs of the low-pass filter 11, the signal is applied to the input

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the threshold unit 12, which, depending on the total value of the phase difference, outputs the voltage corresponding to an increase or decrease in the frequency of the controlled oscillator 13. The voltage corresponding to an increase or decrease in the frequency at the output of the threshold unit 12,

1Q appears when the phase difference exceeds a predetermined value. If the phase difference does not exceed this value, then the control voltage at the output of the threshold unit

15–12 is not output, and the controlled oscillator 13 is not controlled.

From the output of the adder 6, the voltage entered; to the input of the comparators 7 and 8, compared with the voltages

2Q corresponding to the maximum and minimum values of the phase difference, respectively, in each comparator 7 and 8. If the output voltage of the adder 6 exceeds one or the other

25 level, the corresponding comparator produces a pulse. It corresponds to the extreme position of the operating point on the control characteristic of the synchronization device, i.e. the maximum or minimum value of the phase difference, the further growth of which would lead to a jump in the operating point for another period of the control characteristic. The jump occurs to that part of the characteristic that corresponds to the appearance of the opposite trimming signal (spurious) of the controlled oscillator 13. In this case, the signals from the comparators 7 and 8 are combined by the OR element 9 and are fed to the input of the shaper 10 which generates a reset pulse dividers 3 and 14 frequencies. They are reset to such a state that the operating point of the synchronization device returns to the middle of the control characteristic, and at the same time, it is not possible to jump to another period and, moreover, to falsely adjust the controlled oscillator 13.

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Claims (1)

Invention Formula 55 Clock synchronization device generators auth. No. 696620, of tI characterized by the fact that, in order to increase the accuracy of synchronization, additionally introduced first and second. 313325544 a swarm of comparators, the inputs of which are a pulse shaper, are turned off to the output of the adder, and the series-connected element OR, the first and second inputs of which are connected to the outputs of the comparators, and the turn of which is connected to the reset inputs of the second frequency divider and the frequency divisor of each of the n channels of syncronization. driver reset pulses, the output of which is connected to the reset inputs of the second frequency divider and frequency divider of each of the n synchronization channels.