SU1243089A1 - Frequency-phase-lock loop - Google Patents

Abstract

The invention relates to radio engineering and can be used in synchronization and demodulation systems of radio receivers and in the forcing of reference frequencies. The purpose of the invention is to increase speed. The device contains two control loops - frequency and phase, / working alternately. The frequency loop is formed by a frequency detector 1, a limiting amplifier 2, the first key 3, an ingrator (I) 4, an adder (c) 5 and a controlled generator (UG) 6. The loop phase is formed by the phase detector 7, the second 8 and the third 9 keys And 4, C 5 and UG 6. Operation switching is performed by the capture sensor 10, which, at absolute detuning values, exceeding the selected threshold level, turns on the frequency loop through key 3, and in the case of small absolute detunings, the phase loop through keys 8 and 9. For account key input 9, providing alternating operation of frequency and 1 phase loops, the speed of the system increases. 1 il. (L Is9 491 with about 00 WITH

Description

The invention relates to radio engineering and can be used in synchronization and demodulation systems of radio-receiving devices, as well as in systems for the formation of basic frequencies.

The purpose of the invention is to increase speed.

The drawing shows the structure of the electrical circuit of the device for frequency auto-tuning of the device.

The device contains a frequency selector 1, a limiting amplifier 2, a first switch 3, an integrator 4, an adder 5, a controlled oscillator 6, a phase detector 7, a second 8 and a third switch 9, and a pickup sensor 10.

The proposed device works as follows.

The device of frequency-phase auto-adjustment contains two control loops - frequency and phase, operating alternately. The frequency loop is formed by frequency detector 1, limiting amplifier 2, first 25 key 3, integrator 4, adder 5 and controlled oscillator 6, and the phase loop formed by phase detector 7, second 8 and third 9 keys, integrator 4, adder 5 30 and controlled oscillator 6 The switching of the operation is carried out by the pickup sensor 10, which, at absolute values of detuning exceeding the selected threshold level, includes a frequency loop, and in the case of small absolute detunings, a phase loop.

When the device is turned on (input signal), the initial absolute detuning value exceeds the threshold level. In this case, the sensor 10 capture captures the control signals, opening the second 8 and third 9 keys and closing the first key 3. The frequency loop is working. The generated error signal from the output of the frequency detector 1 through the amplifier-limiter 2 and the first switch 3 is fed to the integrator 4. By switching on the amplifier-limiter 2 50, the rate of voltage variation at the output of the integrator 4 is constant, i.e. constant speed of the frequency adjustment, since from the output of the integrator 4 through the adder 5 55 the frequency control signal is fed to the controlled oscillator 6. The frequency of the controlled oscillator 6 is shifted

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in the direction of decreasing the frequency detunings at a constant speed, as a result of which a moment comes when the absolute value of the detuning does not exceed the threshold level. At this moment, the pickup sensor 10 inverts the generated commands, as a result of which the loop of the LAP (first key 3) opens, but the control voltage at the output of the integrator 4 is retained, and the loop FAL is switched on by closing the second 8 and third 9 keys. At the same time provide the second key; the arrival of the control voltage from the output of the phase detector 7 to the input of the integrator 4, i.e. The astatism of the FAN system, and by closing the third key 9, the same control voltage is supplied through the adder 5 to the input of the controlled generator 6, i.e. due to the absence of inertia of the links (9 and 6), the stability of the astatic FAP system. The PLL system, which has a large capture band, at the expense of astatism completely removes both the frequency and phase mismatch, as a result of which the synchronism regime occurs.

Due to the alternate operation of the loop of the FAP and the FAP increases the speed of the system. Indeed, when large frequency detunings take place, the CHAP system does not interfere with the beat on the output of the phase detector, since the keys 8 and 9 are open. This increases the speed of trimming in the BREW mode and improves the accuracy of the moment of switching from the LAP to the PLL. In addition, in the synchronization mode, the CHAP system is turned off, which improves the spectral purity of the output oscillations. At the same time, the capture sensor 10 discriminates the absolute value of the frequency detuning by comparing it with a threshold value and produces a control action.

Claims (1)

Invention Formula A frequency-phase locked loop device containing a frequency detector connected in series, the first input of which is the device input, the limiting amplifier, the first key, the integrator, the adder, the controlled oscillator, the output of which is connected to the second input 3 1243089 frequency detector, phase detector-tector, similar to those torus, the second input of which is connected, which, in order to improve speed, to the input of the device, and the second key, between the output of the phase detector and the output of which is connected to the input of the II input of the accumulator, the third and a capture sensor, s key, the control input of which is connected to the frequency control output of the second key control.