SU926769A1 - Phase-lock loop with synchronism indication - Google Patents

Description

The invention relates to radio engineering and can be used in search and adaptive frequency-tuning systems.

A device is known phase locked loop (PLL) with yn dika The cylinder ⁵ s synchronism, comprising the combined primary and secondary circuits to the inputs of the phase-locked loop, each of which is formed as a ring connected in a controlled ^'0 trolled oscillator, phase detector and low pass filter frequencies, as well as connected in series with an additional low-pass filter and a threshold element [1].

However, this device has a large inertia indication of synchronism.

The purpose of the invention - a reduction of inertia ~ _m tsionnosti matching display.

This goal is achieved by the fact that in the phase-locked loop device with a synchronism indication, containing the main and auxiliary input phase locked loops combined at the inputs, each of which is made in the form of a controlled oscillator, phase detector and low-pass filter connected in a ring, as well as connected in series an additional low-pass filter and a threshold element, a subtractor is introduced, the inputs of which are connected to the outputs of the corresponding low-pass filters of the phase a loops in frequency tuning, and the output to the input of an additional low-pass filter.

In FIG. 1 shows a structural electrical diagram of the proposed device; in FIG. 2 - synchronism ranges of the PLL and the synchronism indication range; in FIG. 3 ~ discriminating characteristics of PLL circuits.

The PLL device with the indication of synchronism contains the main and auxiliary additional filter 10 and the threshold element 11. The following is the difference between the nominal PLL circuits 1 and 2, including the controlled oscillators 3 and 4 connected to the ring, phase detectors 5, 6 'and lower filters 7 and 8 frequencies, subtractor 9, low frequencies

The device at once.

Due to the frequencies of the controlled oscillators 3 and 4! By the value Af, the synchronism ranges of the main and auxiliary loops 1 and 2 of the PLL also turn out to be shifted between each other by the value Af, (fig.2d, B). At the same time, in the steady state, each kohtvd PLL is a frequency discriminator with zero discriminatory characteristics determined by the nominal frequencies of the controlled oscillators 3 and 4, respectively. Due to the displacement of the nomi-. at the frequency of the controlled oscillators 3 and 4, the initial detuning in both PLL loops also differs by the value of A f, which with linear discriminating characteristics of the PLL loops (Fig. 3) in the synchronism mode causes a difference in the control orders by the value AU = S Δ f, where -] the steepness of the discriminatory characteristics.

From the output of the subtractor 9, a voltage of magnitude & U passes through an additional low-pass filter 10 to the first input of the threshold element 11, the second input of which is supplied with a reference voltage level of the threshold Uo, which is less than less than = S- d £, the device indicates synchronism in the PLL system.

The synchronism indication range is determined by the overlapping region of the synchronization ranges of the primary and secondary PLL loops (Fig. 2 $). In the absence of synchronism, the average difference between the control voltages is always zero and does not exceed the reference level of the threshold element 11 - U _e .

For stable operation of the device, it is required to provide an approximate pos ..

the constant value of AU for any initial detuning, which can easily be achieved by using phase detectors and controlled generators with linear characteristics. An additional low-pass filter 10 has a low inertia and can be excluded altogether if low-pass filters with sufficient suppression characteristics are included in the PLL circuits 1 and 2. In this case, the device is practically inertialess, since it indicates synchronism almost immediately after the establishment of synchronism in. both PLL loops.

The proposed device has a significantly lower inertia, as a result of which it can be effectively used to detect a signal in frequency-locked loop systems operating on a pulsed pilot signal, and also to indicate the presence of synchronism in search and adaptive frequency-locked loop systems.

Claims (1)

 FIELD OF THE INVENTION The invention relates to radio engineering and can be used in search and adaptive automatic frequency control systems. It is known a phase locked loop (PLL) with synchronization indication, containing the main and auxiliary loops connected to the inputs of the phase locked loop, each of which is made up of ring controlled variable oscillator, phase detector and low pass filter, as well as connected successively an additional low-pass filter and a threshold element. However, this device has a large inertia of synchronism indication. The purpose of the invention is to reduce the inertia of synchronization indication. This goal is achieved by the fact that the device has a phase locked loop with a synchronism indication. containing the main and auxiliary phase-locked frequency control terminals, each of which is designed as ring-connected controlled oscillator, phase detector and low-pass filter, as well as an additional low-pass filter connected in series and a threshold element, a subtractor is introduced, inputs which is connected to the outputs of the corresponding low-pass filters of the phase locked loops, and the output to the input of the additional low-pass filter. FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - synchronization ranges of the PLL circuits and the synchronism indication range; in fig. 3 discriminatory characteristics of the PLL. A synchronized phase-locked PLL device contains the main and auxiliary circuits 1 and 2 of the PLL, including 8 loop coupled oscillators 3 and 5 phase detectors 5 6 and low pass filters 7 and 8, subtractor 9, additional low pass filter 10, and threshold element 11 The device works as follows. Due to the difference between the nominal frequencies of the controlled oscillators 3 and the magnitude of Af, the synchronism ranges of the main and auxiliary circuits 1 and 2 of the PLL are also shifted by themselves by the magnitude A, (Fig.2q, B). At the same time, in the established mode, each KOHTVD PLL is a frequency discriminator with zero discriminatory characteristic, defined by the nominal frequencies of the controlled oscillators 3 and D, respectively. Due to the shift of the nominal frequencies of the controlled oscillators 3 and (4 initial detuning in both PLL loops also differs by A, which, with linear discriminatory characteristics of the PLL loops (Fig. 3), in the synchronization mode causes a difference in the control gains by the &;. and SAf, where the slope of the discriminatory characteristic. From the output of the subtractor 9, the voltage of magnitude A and through the additional low-pass filter 10 is fed to the first input of the threshold element 11, to the second input of which a specific level is applied The threshold value Uo is the smallest, 4eMuU- S l, the device indicates the synchronization in the PLL. The indication range of the synchronism is determined by the area of overlap of the synchronization ranges of the main and auxiliary PLL circuits (Fig. 21). is always zero and does not exceed the reference level of the threshold element 11 UQ. For stable operation of the device / it is necessary to provide an approximate value of AU for any initial detunings that it is easy for Mt / em to be done The use of phase detectors and controlled oscillators with linear characteristics. The additional low-pass filter 10 has low inertia and can be eliminated altogether if low-pass filters with sufficient suppression characteristics are included in PLL circuits 1 and 2. At the same time, the device is practically inertia-free, since it indicates synchronism almost immediately after establishing synchronism. both PLL loops. The proposed device has a significantly lower inertia, so that it can be effectively used to detect a signal in auto-tuning systems often running on a pulsed pilot signal, as well as to indicate the presence of synchronism in search and adaptive auto-tuning systems. The invention The phase-locked loop with synchronization indication, containing the main and auxiliary phase-locked loops of the phase, each of which is designed as connected in a ring controlled oscillator, phase detector and low-pass filter, as well as connected successively additional low-pass filter frequency and threshold element, in that, in order to reduce the inertia of indica; synchronization, it introduced a subtractor, the inputs of which are connected to the outputs of the corresponding low-pass filters of the phase locked loops, and the output to the input of the additional low-pass filter. Sources of information taken into account in the examination of K Patent COW No. 38930 42, cl. 311-55, 1975 (prototype). l ///////////// 7 //////// FIL.2  tonatyf FLA iene 9 meMmt & ffotunty /