KR20000019406A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: A Phase Locked Loop(PLL) circuit is provided to reduce a locking time independent of a phase difference size by using two different pumping circuits. CONSTITUTION: The PLL circuit comprises: a phase detector(202) for generating a first pumping-up signal or a first pumping-down signal if a phase difference is larger than a predetermined size and generating a second pumping-up signal or a second pumping-down signal if a phase difference is smaller than the predetermined size; a first charge pumping circuit(204) for performing pumping-up according to the first pumping-up control signal and performing pumping-down according to the first pumping-down control signal; a second charge pumping circuit(205) for performing pumping-up according to the second pumping-up control signal and performing pumping-down according to the second pumping-down control signal; a low pass filter(206) for performing a low-pass filtering to generate a direct voltage; and a demultiplexer(210) for demultiplexing the frequency of output signal to generate an input signal.

Description

Phase locked loop circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronous loop circuit, which feeds back a frequency of an output signal to an input to reduce a phase difference from a reference signal.

The phase synchronization loop circuit is a circuit for matching the phase of the output signal with the phase of the reference signal. The basic concept of the phase-locked loop circuit is to feed the output signal back to the input to detect the phase difference with the reference signal, and gradually reduce the phase difference between the reference signal and the input signal by controlling the oscillator circuit to be inversely proportional to the detected phase difference.

Fig. 1 shows a block diagram of such a conventional phase locked loop circuit.

The reference signal f11 and the input signal f12 are input to the phase detector 102. The reference signal f11 is a signal having a constant frequency, and the input signal f12 is a signal to which the final output of the phase-locked loop circuit of FIG. 1 is fed back. The phase detector 102 detects a phase difference between two input signals and selectively generates a pumping up control signal UP and a pumping down control signal DN according to the detected phase difference.

The pumping up control signal UP is a signal generated when the phase of the reference signal f11 precedes the phase of the input signal f12. The pumping-up operation of the charge pumping circuit 104 is performed by this pumping-up control signal UP.

The pumping down control signal DN is a signal generated when the phase of the input signal f12 precedes the phase of the reference signal f11. The pumping down operation of the charge pumping circuit 104 is performed by the pumping down control signal DN.

The charge pumping circuit 104 generates a predetermined pumping voltage V11 by performing a pumping up operation or a pumping down operation according to the pumping up control signal UP or the pumping down control signal DN described above. The pumping voltage V11 is input to the low pass filter 106. The low pass filter 106 filters the input pumping voltage V11 to generate a DC voltage V12 of a predetermined level. The DC voltage V12 generated in the low pass filter 106 is input to the voltage controlled oscillator 108. The voltage controlled oscillator 108 generates an oscillation signal proportional to the level of the DC voltage V12.

The oscillation signal generated by the voltage controlled oscillator 108 is the output signal f13 of the phase locked loop circuit of FIG. In addition, the output signal f13 is divided by the frequency divider 110 at a predetermined frequency and fed back to the input signal f12 of the phase detector 102 described above.

The phase difference between the reference signal f11 and the input signal f12 gradually decreases through the series of processes described above, and the time required for the phase difference between the reference signal f11 and the input signal f12 to fall within the tolerance. This is called locking time.

This locking time depends on the overall operating characteristics of the phase locked loop circuit, but in particular depends largely on the pumping capability of the charge pumping circuit 104. In addition, when the phase difference between the reference signal f11 and the input signal f12 is very large, the load of the charge pumping circuit 104 is greatly increased to further increase the locking time. If the pumping capability of the charge pumping circuit 104 is increased, a very large pumping operation is performed at this time even when the phase difference is small, making it difficult to precisely control the phase difference.

Accordingly, an object of the present invention is to provide two or more charge pumping circuits having different pumping capacities so that a pumping operation having an appropriate size is performed according to the magnitude of the phase difference between the reference signal and the input signal.

The present invention for this purpose comprises a phase detector, first and second charge pumping circuits, a low pass filter, a voltage controlled oscillator, and a divider.

The phase detector generates one of the first pumping up control signal and the first pumping down control signal when the phase difference between the reference signal and the input signal is greater than or equal to a predetermined magnitude, and the second pumping up control signal and the second pumping if the phase difference is less than or equal to the predetermined magnitude. Generate one of the down control signals.

The first charge pumping circuit performs a pumping-up operation of a predetermined size or more by the first pumping-up control signal, and performs a pumping-down operation of a predetermined size or more by the first pumping-down control signal.

The second charge pumping circuit performs a pumping-up operation of a predetermined size or less by the second pumping-up control signal, and performs a pumping-down operation of a predetermined size or less by the second pumping-down control signal.

The low pass filter generates a predetermined level of DC voltage by low pass filtering the output of the first charge pumping circuit and the output of the second charge pumping circuit.

The voltage controlled oscillator controls the oscillation operation by the level of the DC voltage to generate an output signal of a predetermined frequency.

The divider divides the frequency of the output signal into a predetermined magnitude to generate an input signal and feed it back to the phase detector.

1 is a block diagram showing a conventional phase locked loop circuit.

2 is a block diagram showing a phase locked loop circuit according to the present invention;

Explanation of symbols on the main parts of the drawings

102, 202: phase detectors 104, 204, 205: charge pumping circuit

106, 206: low pass filter 108, 208: voltage controlled oscillator

110, 210: Divider f11, f21: Reference signal

f12, f22: input signal f13, f23: output signal

The preferred embodiment of the present invention thus made will be described with reference to FIG. 2 as follows. 2 is a block diagram showing a phase locked loop circuit according to the present invention.

The reference signal f21 and the input signal f22 are input to the phase detector 202. The reference signal f21 is a signal having a constant frequency, and the input signal f22 is a signal to which the final output of the phase-locked loop circuit of FIG. 2 is fed back.

The phase detector 202 detects a phase difference between the two input signals and generates a predetermined pumping control signal according to the detected phase difference. When the phase difference between the reference signal f21 and the input signal f22 is equal to or greater than a predetermined size, one of the first pumping up control signal UP_S and the first pumping down control signal DN_S is generated. On the contrary, when the phase difference is less than or equal to a certain magnitude, one of the second pumping up control signal UP_W and the second pumping up control signal DN_W is generated.

If the phase difference detected by the phase detector 202 is greater than or equal to a predetermined magnitude, neither the second pumping up control signal UP_W nor the second pumping down control signal DN_W is generated. In contrast, when the detected phase difference is equal to or less than a predetermined magnitude, neither the first pumping up control signal UP_S nor the first pumping down control signal DN_S is generated.

There are two charge pumping circuits of the present invention shown in FIG.

The first charge pumping circuit 204 performs a pumping-up operation of a predetermined size or more by the first pumping-up control signal UP_S, and performs a pumping-down operation of a predetermined size or more by the first pumping-down control signal DN_S. .

The second charge pumping circuit 205 performs a pumping-up operation of a predetermined size or less by the second pumping-up control signal UP_W, and performs a pumping-down operation of a predetermined size or less by the second pumping-down control signal DN_W. Conduct.

The above pumping up and pumping down operations of the first charge pumping circuit 204 and the second charge pumping circuit 205 are a pumping operation of a magnitude proportional to the phase difference detected by the phase detector 202. .

That is, the designer prepares a criterion of 'large phase difference' and 'small phase difference' and applies it to the phase detector 202 to apply the first pumping up control signal UP_S and the first pumping down control signal DN_S and the second. Generation criteria of the pumping-up control signal UP_W and the second pumping-down control signal DN_W are provided.

In addition, the criterion for distinguishing the magnitude of the phase difference described above is a criterion for determining the pumping capability of the first charge pumping circuit 204 and the second charge pumping circuit 205. That is, when the appropriate pumping control signal is generated by the predetermined phase difference, giving the first and second charge pumping circuits 204 and 205 a pumping capability capable of generating the pumping voltage required to reduce the detected phase difference. It is a standard for it.

The pumping voltage V21 generated in the first charge pumping circuit 204 or the second charge pumping circuit 205 is input to the low pass filter 206.

The low pass filter 206 low pass filters the output of the first charge pumping circuit 204 or the output of the second charge pumping circuit 205 to generate a DC voltage V22 of a predetermined level. The DC voltage V22 generated in the low pass filter 206 is output to the voltage controlled oscillator 208.

The voltage controlled oscillator 208 controls the oscillation operation by the level of the DC voltage V22 to generate an output signal f23 of a predetermined frequency. That is, an oscillation signal having a frequency proportional to the voltage level of the DC voltage V22 is generated. This oscillation signal is the output signal f23 of the phase locked loop circuit of FIG.

In addition, the output signal f23 is fed back to the above-described phase detector 202 as the input signal f22 via the divider 210. The divider 210 divides the frequency of the output signal f23 into a predetermined magnitude to generate an input signal f22 and feed it back to the phase detector 202.

Therefore, the present invention includes two or more charge pumping circuits having different pumping capacities so that a pumping operation having an appropriate magnitude is performed according to the magnitude of the phase difference between the reference signal and the input signal, thereby greatly reducing the locking time regardless of the magnitude of the phase difference. At the same time, it is possible to control very precise phase difference, which greatly reduces the magnitude of the allowable phase error.

Claims (5)

In the phase locked loop circuit, If the phase difference between the reference signal and the input signal is greater than or equal to a predetermined magnitude, one of the first pumping up control signal and the first pumping down control signal is generated. If the phase difference is less than or equal to the magnitude, the second pumping up control signal and the second pumping down control are generated. A phase detector for generating one of the signals; A first charge pumping circuit in which a pumping-up operation of a predetermined size or more is performed by the first pumping-up control signal, and a pumping-down operation of the predetermined size or more is performed by the first pumping-down control signal; A second charge pumping circuit configured to perform a pumping-up operation of the predetermined size or less by the second pumping-up control signal and to perform a pumping-down operation of the predetermined size or less by the second pumping-down control signal; A low pass filter for low pass filtering the output of the first charge pumping circuit and the output of the second charge pumping circuit to generate a DC voltage of a predetermined level; A voltage controlled oscillator for generating an output signal of a predetermined frequency by controlling the oscillation operation by the level of the DC voltage; And a divider for dividing the frequency of the output signal into a predetermined magnitude to generate the input signal and feed it back to the phase detector. The phase locked loop circuit of claim 1, wherein both the second pumping up control signal and the second pumping down control signal are not generated when the phase difference detected by the phase detector is equal to or greater than the predetermined magnitude. The phase locked loop of claim 1, wherein the first pumping-up control signal and the first pumping-down control signal are not generated when the phase difference detected by the phase detector is equal to or less than the predetermined magnitude. The phase locked loop circuit of claim 1, wherein the pumping-up operation and the pumping-down operation of the predetermined size or more performed in the first charge pumping circuit are pumping operations having a magnitude proportional to the phase difference detected by the phase detector. The phase locked loop circuit of claim 1, wherein the pumping-up operation and the pumping-down operation below the predetermined size of the second charge pumping circuit are pumping operations having a magnitude proportional to the phase difference detected by the phase detector.