SU475562A1 - Automatic frequency control device - Google Patents

Description

one

The invention relates to the field of electrical measuring equipment and can be used to improve the noise immunity of devices, in particular digital voltmeters.

There are various systems of automatic frequency control. Phase-locked loops are most commonly used in digital voltmeters. These systems have an important advantage over other known systems: the residual difference between the reference and adjustable frequencies is zero.

For a known automatic frequency control device, non-linearity (deviation of the instantaneous value) of the frequency of the controlled oscillator during the measurement interval is characteristic, which leads to non-linearity of the digital voltmeter scale. This non-linearity is caused by the pulsations of the output voltage of the filter, which are due to the insufficient value of the constant time of the filter. As the time constant increases, the pulsations decrease and the non-linearity of the frequency decreases. However, an increase in the filter time constant is undesirable, since it reduces the system speed and significantly reduces the setting range (adjustable frequency range).

The purpose of the invention is to reduce the nonlinearity of the frequency of the controlled oscillator without

reducing the setting and speed of the automatic frequency control system.

This is achieved by the fact that in the scheme, which is a closed circuit of the phase

the detector, a filter, a controlled oscillator, and a frequency divider, include two parallel channels connecting the filter output to the input of the controlled oscillator. Each channel contains a memory capacity, connected

through the input key to the output of the filter, and through the output key to the input of the controlled generator. In this case, a trigger with a counting input is connected to the output of the frequency divider, the direct output of which is connected to the control circuits of the input key of one channel and the output key of another channel, and the inverse output of the trigger is connected to the control circuits of the other two keys. FIG. 1 shows the block diagram of the proposed automatic frequency control device; in fig. 2, a-d, shows time diagrams of the device operation.

The proposed device contains a phase detector 1, the output of which is connected to

the input of the filter 2. The output of the filter 2 is connected to the input of the controlled generator 3 by two parallel channels. Each channel consists of a memory capacity of 4 (or 5) connected to the output of filter 2 through the input

key 6 (or 7) and to the input of the controlled generator 3 through the output key 8 (or 9). The output of the controlled oscillator 3 is connected to the output of the device and through frequency divider 10 to one of the inputs of the phase detector 1. The other input of the phase detector is connected to the input of the device. In addition, trigger 11 is connected to the output of the frequency divider with a counting input, the forward output of which is connected to the control circuits of the keys b and 9, and the inverse input of the trigger 11 is connected to the control circuits of the keys 7 and 8.

The signals of two frequencies are fed to the inputs of the phase detector: a reference one (from the device input) and a tunable one (from the output of frequency divider 10). The output of phase detector 1, averaged by filter 2, is a function of the difference between these frequencies. Due to the finite time constant of the filter 2, its output voltage contains pulsations superimposed on the constant component (Fig. 2, a). This voltage is applied to keys 6 and 7. In time TI, keys 6 and 9, for example, are closed, and 7 and 8 are open. Then the voltage from the output of the filter 2 through the closed key 6 passes to the capacity of memory 4, which monitors this voltage and fixes its value at the moment of time i (Fig. 2, b). The input voltage of the controlled generator 3 at this time interval is supplied with a constant voltage fixed by the memory capacitance 5. In the time interval Tz, keys 6 and 9 are open, keys 7 and 8 are closed, and the output voltage of the filter 2 at time / 2 is fixed storage capacity 5 (Fig. 2, c). In the same period of time, the voltage, fixed by the capacitor of us 4 in the previous interval of time TI, is fed to the input of the controlled generator 3 (Fig. 2, b).

Thus, at any point in time, a constant voltage devoid of pulsations is applied to the input of the generator to be regulated. Controlled oscillator output

through the frequency divider 10 is applied to the inputs of the phase detector and trigger 11. The trigger controls the operation of keys 6-9 so that keys 6 and 9 work in antiphase with the keys

7 and 8.

In comparison with the known device, the proposed device reduces the non-linearity of the frequency of the controlled oscillator by a factor of 1000, without reducing the setting range and speed of the system.

Subject invention

An automatic frequency control device containing a series-connected phase detector, a filter, a controlled oscillator and a frequency divider, the output of a frequency divider connected to a second input of the phase detector, characterized in that, in order to reduce the non-linearity of the controlled oscillator, it is equipped with two memory devices , two input keys, two output keys and a trigger, with the first input and output keys connected in series, the input of the first input key being connected by To the filter output, and the output of the first output key to the input of the controlled generator, the second input and output keys

also connected in series so that the input of the second input key is connected to the output of the filter and the output of the second output key to the input of a controllable oscillator, while the control inputs of the first input and

The second output keys, as well as the second input and first output keys are combined and connected respectively to the first and second outputs of the trigger, the input of which is connected to the output of the frequency divider, the first and second memory devices being connected respectively between the outputs of the first and second input keys, and the device case .

Output

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T2

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