SU813676A1 - Frequency multiplier - Google Patents

Description

(54J MOTIVITY FREQUENCY

The invention relates to radio engineering and can be used as a frequency multiplier in devices for forming a discrete set of frequencies. Frequency multipliers based on pulsed-phase-locked loop devices are known, including a tunable oscillator connected to a ring, a pulse-phase detector, a memory device, a low-pass filter, a control element. The second input of the pulse-phase detector receives a sequence of reference pulses, the output of the adjustable oscillator is the output of the device. The disadvantage of these devices is the low stability of the output oscillation phase of the adjustable oscillator, due to the insufficient slope of the phase discriminator at the point of stable equilibrium of the feedback ring, as well as the displacement of the phase discrimination point itself under the influence of destabilizing factors on the key phase detector. The closest to the one proposed is a frequency multiplier containing a series-connected low-pass filter, a control element, a tunable oscillator, a key phase detector and a memory device 2. .. However, such a multiplier does not provide sufficient phase multiplication accuracy. Detectors have significant zero drift. The purpose of the invention is to improve the accuracy of phase multiplication. To achieve this goal, in the frequency multiplier, containing a series-connected low-pass filter, a control element, a tunable oscillator, a key phase detector and a memory device, serially connected band-pass filter, amplifier and phase-sensitive sensor are inserted between the memory output and the filter input input. rectifier, to the other input of which the output of the entered frequency divider is connected by two, the input of which is combined with another input of the key phase detector and is The input reference signal are frequency multiplier.

The drawing shows a structural electrical circuit of the proposed frequency multiplier.

The frequency multiplier contains memory 1, band-pass filter 2, amplifier 3, phase-sensitive controller 4, low-pass filter (LPF) 5, control element adjustable oscillator 7, key phase detector 8, frequency divider 9 by two.

The frequency multiplier works in the following way.

At one input of the key phase detector 8 receives a sequence of reference pulses E (t), the duration and repetition period of which, respectively, C and T, with Ci.T. The second input of the key phase detector 8 receives the signal of the adjustable oscillator 7.

The product of nonlinear conversion at the output of the key phase detector 8 when performing the ratio

- (k-i), (i)

t

where k is any of the series k 0,1,2, ..., contains a component with frequency F 2y and amplitude proportional to s i p P where F is the phase of the signal of the adjustable oscillator 7 at the moments of arrival of reference pulses.

After this component is isolated by the bandpass filter 2 and amplified by amplifier 3, the error signal is fed to the input of the phase-sensitive rectifier 4, to the second input of which the reference signal is output from the divider 9 frequency two. From the output of the phase-sensitive rectifier 4 through the low-pass filter 5, the voltage, which is proportional to sin-p, and the polarity is determined by the signal mismatch, is fed to the control element b, which adjusts the frequency of the generator 7, i.e. PLL loop closed. In synchronization mode, the frequency of the adjustable oscillator 7 satisfies condition (l). In this case, at the output of amplifier 3, the amplitude of the frequency signal F f is zero at F f}% regardless of the instability of the parameters of the key phase detector 8 and amplifier 3. When the oscillation phase of the adjustable oscillator 7 deviates from F pTS under the influence of destabilizing factors, the PLL ring reduces it deviation to the value determined by the transmission coefficient of this ring. The increase in the slope of the phase discrimination characteristic at the point of stable equilibrium of the PLL ring in this frequency multiplier is not accompanied by a shift of the point of stable equilibrium under the effect of destabilizing factors characteristic of known devices, since at the output of amplifier 3 the amplitude of the frequency signal f 2Т is equal to zero regardless of the instability of the parameters of the key phase detector 8 and amplifier 3. The relative drift of the parameters of the phase-sensitive rectifier 4 can be largely compensated. velicheniem amplitude of the signal applied to its input. The phase instability of the amplifier 3 in this case leads only to a change in the steepness of the characteristic of phase discrimination, without causing a displacement of the very point of discrimination.

Thus, in the proposed frequency multiplier, the steepness of the phase discrimination characteristic of the PLL ring is increased, without causing a displacement of the discrimination point characteristic of known devices. This increases the phase stability of the oscillating oscillator 7 and, consequently, the accuracy of the phase multiplication.

Claims (2)

1. Shahgild V.V. - and others. Phase locked loop systems. M., St. Don, 1972, p. 339-340, 411. 2. Belotsvetov Yu. V., Terentyev B.P. Analysis of multiple frequency conversion circuits with a pulse-phase detector. - Electroslap, 1959, No. 9, with. 25-30 (prototype).