SU1228248A1 - Multichannel device for generating delayed pulses - Google Patents

Abstract

The invention relates to computing and impulse technology. It can be used to obtain a sequence of pulses of adjustable duration shifted by a control time interval in one channel relative to another. The purpose of the invention is to expand the field of application of the device by obtaining pulses of adjustable duration with adjustment of the time interval between pulses in different channels. To achieve this goal, two elements AND 8 and 9, two, are introduced into the device. element OR 3 and 10, trigger 7 and frequency divider 2. The device also contains a frequency divider 1, output triggers (4-1) - (4-N), amplifiers (5-1) - (5-i), software-distribution block 6, the time delay of the triggering of the trigger 7 is formed by a divider 1 or 2. 2 sludge. i (LU, 00, 00

Description

The invention relates to computational and pulsed techniques and can be used to obtain a sequence of pulses of adjustable duration shifted by a controlled time interval in one channel relative to another.

The purpose of the invention is to expand the field of application of the device by obtaining pulses of adjustable duration with adjustment of the time distance between pulses in different channels.

Fig. 1 shows a block diagram of the device; Fig. 2 is a diagram explaining its operation.

The multichannel device for generating delayed pulses contains frequency dividers 1 and 2, the corresponding control inputs of which are combined and connected to the inputs of the OR element 3, to the corresponding inputs of the output triggers (4-1) - (4-N) and through amplifiers (5-1 ) - (5- h) to the outputs of the software distribution block 6, one input of which is connected to the output of frequency divider 2, and the other is the starting input of the device. The output of element OR 3 is connected to one input of trigger 7, and the other input of which is connected to the output of splitter 2 frequencies, and the zero and single outputs are connected respectively to one input of elements AND 8 and 9, the other inputs of which are combined and are the input of the device the output element And 8 is connected to the input of the splitter 1 frequency, and the output of the element And 9 is connected to the input of the element OR 10, the other input of which is connected to the output of the splitter 1 frequency, and the output is connected to the input of the splitter 2 frequency. The outputs of the output triggers (4-1) to (4-n) are the outputs of the device.

A multichannel device for generating delayed pulses operates as follows.

The trigger signal arriving at the starting input of the device brings the unit to the first bit of the software distribution block 6. From its first input through the amplifier 5-1 this single signal goes to the input of the element OR 3, as well as to the first inputs of frequency dividers 1 and 2 . The software-distribution block is made, for example, in the form of a shift register, Divide w 1 and 2 frequencies

five

0

five

0

five

0

five

0

five

with variable division ratio. Each of the inputs of the divider is connected to those bits in which it is necessary to add a unit to obtain the required delay. Divider 1 delay value

ts-tb-iU-Kj,

t is the period of the impulses arriving at the device's clock input,

1 the difference between the capacitor K divider 1 and the number K. which is entered into it, - for the divider 2, the delay value

(M-Mj ,,,

where T is the period of filling the divisor .-, L is the difference between the capacity M of the divider 2 and the number M, which is entered into it. The total delay t of the generated pulses or their duration is equal to

 V -, + t.

From the output of the VDI 3 element, the signal arrives at the input of the trigger 7 and sets it to one state. In this case, the AND 8 element is opened and the clock with a period begins to arrive at the input of divider 1. After the arrival of I pulses, the first pulse appears at the output of which is fed through the element OR 10 to the input of the divider 2.

Through the pulses received at the input of the divider 2, a pulse appears at its output, which is fed to the shift input of the software-distributing unit 6 and to the reset input of the trigger 7, the unit stored on the start bus is moved from the first bit software distribution block in the second. Like E described above, the signal 6 from its second input through the amplifier 5-2 goes to the second control, inputs of dividers 1 and 2, as well as through the element OR 3 and the trigger input 7, In addition, this signal goes to the input setting the output trigger 4-1, sets it to state 1 and, thus, the leading edge of the first pulse is formed in the first channel. The end of this pulse depends on the numbers entered in dividers 1 and 2 through their second control inputs. After the appearance of the signal on b0: ode of the second divider 2 and its arrival at the input of the software distribution block 6, 1 in this

J

the block is moved from the second bit to the third, and the trigger 7 is set to O with the same signal. A single signal from the third output of block 6 through the amplifier 5-3 enters the reset input of the output trigger 4-1 and brings it to the zero state, thereby the leading edge of the first pulse is formed in the first channel. The same signal arrives at the third control inputs of dividers 1 and 2 and writes new numbers into them that determine the time distance between the falling edge of the first channel and the leading edge of the second channel, after which 1 moves in the software-distribution block 6 from the third bit to the fourth. A single signal from the fourth output of block 6 through the 5-A amplifier enters the single input of the trigger 4-2 and sets it to the single state, thereby forming the leading edge of the pulse in the second channel, and writes down the fourth control inputs of the dividers 1 and 2 , determining its duration. Next, the operation of the device is repeated. In this case, pulse pulses of a given duration with predetermined time distances between them are formed sequentially through the channels.

In order to regulate the time distance between the falling edge of the pulse in the last channel and the leading edge of the pulse in the first channel, for example, for the case of cyclic operation of the device, the first output of block 6 may not be connected to the inputs of the output flip-flops.

If the trigger 7 is not to be set to one in order to form the required delay value, then the corresponding input of the OR 3 element may not be connected to the output of the corresponding amplifier (5-1) - (5-h). The value of

282484

delays will be determined only by a divider 2.

The delay can also be generated only by the divider 1, with all units being written to divider 2.

Claims (1)

Invention Formula JQ Multichannel device for the formation of delayed pulses, containing a frequency divider, output triggers and a software distribution block, whose input is connected to the output of the frequency divider, and via the amplifiers connected to the control inputs of the frequency divider and to the corresponding output inputs triggers whose outputs are The outputs of the device, characterized in that, in order to expand the functionality by obtaining pulses of adjustable duration with adjustment of the time-to-distance distance of pulses in different channels, two elements AND, two elements OR, a trigger and a second frequency divider are introduced into it, and the corresponding control inputs of the frequency dividers are combined and connected to the inputs of the first OR element, the output of which is connected to one of the trigger inputs, the other input of which is connected to the input of the software distributor ny block, and 5 outputs are connected to one of the inputs of the corresponding AND elements, the other inputs of which are combined and are the clock input of the device, and their outputs are connected respectively to the input of the second frequency divider and to one of the inputs of the second WIT element, the other input of which is connected to the output of the second frequency divider, and the output is connected to the input of the frequency divider, with the other input of the software distribution block being the starting input of the device. 0 FIG. 2 Editor Compiled by A.Titov Tehred I.Veres Order 2296/57 Edition 816 Subscription VNII11I State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader K. Demchik