SU834846A1 - Pulse train generator - Google Patents

Description

(54) PULSE SERIES GENERATOR

one

The device relates to a pulse technique and can be used to form time intervals in a measurement technique, in a pulse radio communication, in various timing systems, in studies in nuclear physics.

A device for forming a series of rectangular pulses is known, comprising an adder, a set of switches, a group of pulsed potential gates, a trigger, a group of OR elements, a delay element 1.

The drawback of the device is the lack of adjustment of the time intervals between pulses in a series and the considerable dimensions of the device, determined by the need to use a large number of elements to obtain N pulses in a series.

The closest to the proposed generator of a series of pulses contains a software device, an element I, a counter, a unit for recording units, a delay line, a switch, a shift register 2.

The disadvantages of the known former are the lack of smooth adjustment (with discreteness determined by the period

clock pulses) of the period of the output pulses of a series for a given constant volume of the counter, limited range of adjustment of time intervals between pulses in a series, defined, ma - the number of bits of the register, shift and counter, as well as the number of element I. The aim of the invention is to expand the range of regulation time intervals between pulses in a series.

The goal is achieved by the fact that a pulse train generator containing a programmable switch, the outputs of which are connected to the first inputs of an AND block, a pulse counter and a memory block, additionally introduces a pulse counter, an n-bit frequency divider, a control trigger and two elements OR, the inputs of the first of which are connected to the outputs of the block of elements AND, the second inputs of which, except the first, are connected to the outputs of the bits of the n-bit frequency divider, the second inputs of which are connected to the output of the second element OR, the first input of the second OR element is connected to the first inputs of an additional pulse counter and control trigger, the second input of which is connected to the output of an additional pulse counter, the second input of which is connected to the second input of the second OR element and to the output of the main pulse counter, the first input of which is connected to the output of the first the OR input, the second input is connected to the output of the control trigger, and the information inputs of the main pulse counter are connected via a memory block to the discharge outputs of the pulse counter and to discharge dnym inputs programmable switch, the count input n-bit frequency divider is connected to first inputs of the second element block I.

The drawing shows a functional diagram of the pulse train generator.

The generator contains counters 1 and 2 pulses, block 3 of memory, trigger 4 of control, p-bit divider 5 frequencies, elements OR 6 and 7, block 8 elements AND, programmable switch 9, start bus 10, bus 11 clock frequency, output tire 12.

The pulse train generator works in the following way.

In the initial state, the trigger 4 is in the zero state, blocking the counter 2. In the memory block 3, N required delays are recorded. The counter contains the number N, corresponding to the number of necessary delays.

The bus 11 receives clock pulses at the p-bit divider 5 frequencies and at the first input of the first element AND of block 8. At the first inputs of the remaining inputs of block 8 there are pulses from the corresponding outputs of divider 5. To the counting input of the counter 2 through element 7 OR a signal is supplied from one of (Nk-1) elements of AND block 8, on the second input of which there is a resolving potential from switch 9 (on the second inputs of the other N elements and block 8 there are forbidding potentials).

In the programmable switch 9, frequency switching codes are recorded. The output number of the switch 9, on which the resolving potential is present, is determined by the code arriving from the outputs of the counter bits, 1. There are no signals at 10 and 12. When a start pulse is applied to the busbar 10, the counter and (through the element OR 6) frequency dividers 5 are set to zero, trigger 4, release counter 2 also switches to one state. In counter 2 of memory block 3, the code is rewritten corresponding to the value of the first delay, and pulses arrive at its counting input, the frequency of which for a given delay is set from the programmable switch 9 by supplying the second input of the element from block 8 of the resolving potential.

Counter 2 counts the pulses arriving at its counting input. At the moment when the counter 2 counts the recorded number of pulses and is set to zero state, a pulse delayed in time relative to the starting signal appears on its output, which goes to bus 12, to the counting input of counter 1 and to the second input of the element 6 OR. At the outputs of the bits of counter 1, a new code arises, according to which, from block 3 of the memory, the number corresponding to the second delay value is copied into counter 2. The same code is fed to the programmable switch 9. From the output of the element OR 6, the pulse arrives at the inputs of the zero divider 5, resetting them to the zero state. Counter 2 again counts the clock pulses arriving at its counting input. At the moment when the counter 2 counts the recorded number of pulses and sets to the zero state, a pulse delayed in time relative to the pulse of the first delay, which arrives on the bus 12, appears at the output of the counter input and at the second input of the element OR 6 etc. After processing the Nth delay, i.e. after the appearance on the bus 12 of the N-oro pulse, from the output of counter 2, the signal arrives at the counting input of the counter.

At the output of counter 1, a pulse arises, setting trigger 4 to the zero state. When this occurs, counter 2 is blocked and the pulse train generator returns to its initial state, which will remain until the next start pulse arrives.

Thus, at the output of the proposed generator, a series of pulses is produced, the time intervals between which are determined, firstly, by the volume of the counter and, secondly, by the period of the pulses arriving at its counting input. With the same volume of this counter, time intervals between adjacent pulses of a series of different size can be obtained in accordance with the clock frequency value set at the counter input of the counter using a programming switch.

Claims (1)

Invention Formula A pulse train generator containing a programmable switch, the outputs of which are connected to the first inputs of an AND block, a pulse counter and a memory block, characterized in that, by extending the range of time intervals between pulses in a series, a counter is added to it