SU1758886A1 - Device for protecting for burst noise - Google Patents

Description

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(21) 4728592/09 (22) 09.08,89 (46) 08/30/92. Bul Number 32

(71) Taganrog Research Institute of Communications

(72) L.N. Melnikov, L.N. Melnikov and A.V.Margelov

(56) USSR Author's Certificate No. 425386, cl. H 04 L 7/00, 1975.

USSR Author's Certificate No. 629643, cl. H 04 L 1/00. 1978

USSR Author's Certificate No. 1-095427, cl. H 04 L 7/00, 1985. (54) DEVICE FOR PROTECTION AGAINST IMPULSE INTERFERENCE

(57) The invention relates to radio engineering and can be used in discrete information transfer devices. The purpose of the invention is to expand the functionality of the device by the possibility of restructuring the parameters of the input signal. The device for protection against impulse noise contains a counting trigger 6, the element IS-NE 7, the inverter 3 and the counter 4. The goal is achieved by the introduction of two registers 9 and 10, multiplexer 8, control trigger 13 of the elements 14 and 15, the comparison unit 5 and the element EXCLUSIVE OR 2, which provide the recording of parameter codes from an external control device, storing and issuing these codes to the inputs of the comparison unit, leading them one by one to the current codes of the pulse duration and the duration of the pauses. 2 yl

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The invention relates to radio engineering and can be used in various devices for the transmission of discrete information.

A device for protection against impulse noise, containing a delay element on the counting trigger, two elements And a counting trigger. The device eliminates the impulse noise of a false pulse due to the selection of pulses in duration. The duration of the impulse noise is less than the duration of the information of the pulses. However, this device does not exclude interference arising from the fragmentation of impulses (loss of impulse).

A device for protection against impulse noise containing a paired delay element and an OR element is known. The device eliminates impulse noise False impulse, loss of impulse, however, does not provide suppression of multiple impulse noise of both types, because there are no control elements that return it to its original state.

A device for protection against impulse noise, containing a counter, the outputs of which are connected to the inputs of the first and second elements AND-NOT, the output of the first element AND-NOT connected to the output of the device, to the input of the element IL AND-NOT and to the zero input of the counting trigger, clock the input of which is connected to the input of the third NAND element and to the output of the second NAND element, and the zero and single outputs of which are connected respectively to the inputs of the second and third AND AND elements and to the input of the fourth NAND element, the other input of which is connected to the entrance device and the input of the inverter, the output of which is connected to the input of the third AND-NOT element, another input of which is connected to the output of the fourth AND-NOT element, and the output to the input of the first AND-NOT element and to the reset input of the counter, the clock input of which is connected to the clock input of the device and the inputs of the first and second olementosis AND-NOT.

In the prototype device, the multi-input elements AND-HE 3, 7 record the values of the minimum pulse width tmin and the minimum pause duration tmin. Therefore, when the parameters of input information pulses in the device change during operation, it is impossible to change the imini, tnmin values promptly, which is incomplete (ohm.

The aim of the invention is to expand the functionality of the device by the possibility of restructuring

parameters of input information pulses.

This is achieved by the fact that the first and second registers, the first and second elements AND, the control trigger, are entered into the impulse protection device containing the counting trigger, the NAND element, the inverter and the counter whose clock input is the clock input of the device

0 multiplexer, comparison unit and EXCLUSIVE OR element, with the output of the element ELIMINAL OR through the inverter connected to the first counter reset input, the outputs of which are connected to the first group of inputs of the comparison unit, to the second group of inputs the outputs of the first and second registers are connected through a multiplexer the output of the comparison sheet is connected to the first input of the NAND element and to

0 is the input of a counting trigger, the unit output of which is connected to the second input of the NAND element, to one of the inputs of the EXCLUSIVE OR element and to the multiplexer control input, direct and inverse

5 control trigger outputs are connected through the corresponding elements AND to the recording inputs of the first and second registers, whose information inputs are interconnected and are code inputs

0 parameters of the device, the control input of which is the control input of the control trigger, which is connected to the second inputs of the elements I, the setup signal input to the initial state of the trigger

Control 5 is connected to the corresponding counter input and to the single input of the counting trigger and is the input of the setup signal to the initial state of the device, the information input of which is 0 to the other input of the EXCLUSIVE OR element, the clock input of the comparison unit is connected to the clock input of the counter.

Fig, 1 shows a block diagram of the device; Fig, 2 - time diagrams5 we work device

The device contains information input 1, an EXCLUSIVE OR 2 element, an inverter 3, a counter 4, a comparison block 5, a counting trigger 6, an AND-NE 7 element, a multiplex plexor 8, registers 9, 10, inputs of the parameter code of the device 11, a control input of the device 12, control trigger 13, elements AND 14, 15, WMO.E. the signal of resetting the device to the initial state 16, the three-way input of the device 17, the output of the device 18.

The time diagram of Fig. 2 shows the diagrams of the following signals: a - pulses from input 16, b - pulses at input 12, c-pulses at one of the code bits

inputs 11, g - pulses at input 1, d - pulses at the first counter reset, e - pulses at the output of comparing unit 5, W - pulses at a single output of trigger 6, h - pulses at output 18.

Information input device 1 is connected to the input element EXCLUSIVE OR 2, the output of which through inverter 3 is connected to the first reset input of the counter 4, the outputs of which are connected to the first group of inputs of the comparison unit 5, the output of which is connected to the input of the counting trigger 6, and the first input of the element AND-NOT 7, the single output of trigger 6 is connected to the second input of the element AND-NOT 7, to the input of the EXCLUSIVE OR 2 element and to the control input of the multiplexer 8, the first and second group of inputs are connected respectively to the outputs of registers 9,10, information The inputs of which are interconnected and are the inputs of the parameter code of the device 11, the control input of the device 12 is connected to the control input of the control trigger 13 and the second inputs of the elements 14, 15, the first inputs of which are connected respectively to the forward and inverse outputs of the trigger control 13, and the outputs - with the inputs of the register register 10, 9, the installation input to the initial state of the control trigger 13 is connected to the second reset input of the counter 4, to the single input of the counting trigger bis to the input signal to the initial state The device 16, the clock input of the device 17 is connected to the clock inputs of the counter 4 and the comparison unit 5, the output of the element AND-7 7 is connected to the output of the device 18.

The invention can be implemented, for example, on IC series 155.555. Counter 4 and counting triggers 6, 13 are switched on the falling edges of the input pulses. The multiplexer 8 passes to the output a code from register 9 at 1 level at the control input and a code from register 10 at the O level at the control input. Counter 4 counts clock pulses if there is a level 1 on both inputs,

The device is reset to the initial state when a pulse is applied to the reset input 16 (figure 2, a, interval T0-Ti). At the same time, the counter 4 is set to O, the trigger 6 to 1, the trigger 13 to O. When the parallel code tmin is fed to the inputs of the parameter code of the device 11 (figure 2, in, the interval T0-Ti) and the first pulse to the control input of the device 12 (Fig. 2,6, T0-Ti interval) this code is written to the register 9. When the tnmini code is applied to the inputs 11 and the second pulse to the input 12, the tnmini code is written to the register

10. After writing the parameter codes, the device alternately operates in two modes: the duration control mode and the pause control mode.

5 A pulse train is fed to information input 1 (Fig. 2, d). Upon receipt of the first pulse of duration ti tmin, the output of the inverter 3 is set to level 1 {2, d, the interval

10 T0-Ti) and counter 4 starts counting clock pulses, measuring the duration ti. Comparison unit 5 compares codes in

each bar and after counting nmini takto

The 15 output pulses of the code from the outputs of counter 4 are equal to the code tmin, and a pulse is formed at the output of the comparison block 5 (Fig. 2, e, T0-Ti interval). The trigger 6 is switched to the state O (Fig. 2, g, the interval T0-Ti) and

0, a pulse is generated at output 18 (Fig. 2, 3, T0-Ti interval). At the output of inverter 3, a level O is set, which holds the counter 4 in O for the time At ti - tmini before the end of the first pulse.

5 Then, the level 1 is set again at the output of the inverter 3 and the counter 4 starts counting the clock pulses, measuring the pause duration tni. When switching trigger 6 in O, the multiplexer starts

0 to output and register 10 the tnmini code, which is compared with the current counter code 4. If tni tnmini, the output pulse of the comparison unit 5 switches the trigger 6 into 1 and the device is ready to receive the next pulse 5 and operate in the pulse activity monitoring mode. Thus, each time an input pulse with a duration ti tmini arrives at the device input, an output pulse equal in

0 duration of the clock pulse and coinciding with it in phase, which is delayed relative to the leading edge of the input pulse for the time tmmi.

If a pulse arrives, the duration

5 which is less than tmini Gfg.2, e, the second pulse in the interval T0-Ti), it is considered an interference pulse. Counter 4 does not have time to count the nmini pulses, block 5 does not output an output pulse, and trigger 6 remains in 1,

0 therefore, the device does not switch to pause control mode. If several interfering pulses are received, the comparison unit 5 does not emit any output pulses and the trigger 6 remains at 1. In this

In the 5th state, it remains until an impulse is received WITH A DURATION G, tmlnlIf the pause between tni pulses is less than tnrninl, it is considered that the input sequence is distorted by interruption

momentum. In this case, the counter 4 does not have time to count the nmin2 G clock pulses

However, comparison unit 5 does not generate an output pulse, trigger 6 remains in O. The device continues to operate in pause control mode until the next pause between pulses is more than tnminl, after which it switches to pulse control mode.

When the parameters of the input sequence change, the external device in the control issues an installation pulse to the input 16 (figure 2, a, TI), then delivers the parallel code of the parameter tmin2 and the first write pulse to the device input 12 (figure 2.6, interval Ti-T2), after which a parallel parameter code tnmir 2 and a second write pulse are fed to input 12. The duration of the operational tuning in the device is determined by the sequential recording time of three parameters codes from inputs 11 provided that the external device entu supply input 16 to the initial setting pulse state is the current values of these parameters obtained by the measurement, or fed to the control panel by the operator. After the operative adjustment of the parameters, the device processes the input pulse sequence with the changed parameters.

Thus, the invention allows, in comparison with known devices, to reorganize the parameters of the input information pulses.

Claims (1)

The invention device for protection against impulse noise, containing a counting trigger, the element AND-NOT, inverter and counter, clock the input of which is a clock input of the device, characterized in that, in order to expand the functionality of the device by providing the possibility of rearrangement of parameters of input information pulses, the first and second registers, the first and second elements AND, the control trigger, the multiplexer, the comparison unit and the element are introduced EXCLUSIVE IL AND, with the output of the EXCLUSIVE OR element through the inverter connected to the first reset input of the counter, the output of which is connected to the first group of inputs of the comparison unit, to the second the group of inputs of which are connected to the outputs of the first and second registers through a multiplexer, the clock input of the comparison unit is connected to the clock input of the counter, and the output of the comparison unit is connected to the first the input of the NAND element and the input of the counting trigger, a single output of which is connected to the second input of the NAND element, one of the inputs of the EXCLUSIVE OR element and the control input of the multiplexer, the direct and inverse outputs of the control trigger are connected via the corresponding AND elements to the inputs records of the first and second registers, informational inputs of which are interconnected and are the inputs of the parameter code of the device, the control input of which is the control input of the control trigger, which is connected to the second inputs of the first and second elements AND, the setup signal input to the initial state of the control trigger is connected to the second counter reset input and to the single input of the counting trigger and is the initial state input signal device, the information input of which is another input of the EXCLUSIVE OR element. guv five