SU1460721A1 - Multichannel device for priority selection of pulses - Google Patents

Abstract

The invention relates to the field of computing and can be used to organize program interruptions. The purpose of the invention is to reduce the amount of equipment. The device contains an element NOT, two elements AND and channels, and in each channel there are three triggers, six elements AND, two elements OR, an element NOT. The device for each incoming request (the pulse duration can be arbitrary) at the corresponding output selects from such a synchronization frequency a pulse of a positive or negative phase of synchronization. 2 pcs.

Description

The invention relates to computing, in particular, to priority devices, and can be used for organizing program interruptions.

The purpose of the invention is to reduce the amount of equipment.

Fig. 1 shows a block diagram of the device I in Fig. 2, a timing diagram explaining the operation of a multi-channel device for the priority selection of pulses.

The device contains channels 1-3, triggers 4-6, elements AND 7-12, elements OR 13 and 14, elements NOT 15 and 16, elements AND 17 and 18, query inputs 19-21, information outputs 22-24, clock input 25, the first clock output 26 and the second clock output 27.

The device works as follows.

Before starting work, a reset pulse is sent to the common bus (not shown) for resetting triggers 4-6 channels 1-3 and sets the triggers 4-6 of each channel to the initial zero state, forming a continuous transfer circuit (if inputs 21-21 do not not a single request pulse of the synchronization pulses of the negative phase of the signal from input 25 through the element HE 16 and element 17 and the first clock output 26, and the positive signal phase from input 25 through element 18 on the second clock output 27.

Imagine that a request pulse arrived at input 19 at some point in time (on time diagram t) with a duration sufficient to overturn the trigger (in Figure 2 is shaded), and let b 5 be the response delay of the AND, OR, NOT, elements but

W

with:

4 Od O H

Yu

 - trigger trigger delay

As can be seen from the timing diagram, the arrival of the request signal coincides with the positive pulses of the negative phase of the sync series. For convenience, the following condition is positive: the phase of the synchronization pulses arrives at the clock input of the device 25, F, and the phase of the synchronization pulses from the output of the HE element is 16 F. The setting

trigger 6 of channel 1 into a single state with a positive, phase F pulse through an AND 10 element, channel trigger 6 prepares an AND channel element for its channel for opening and maintains a single level through an OR 13 element at the outputs of the AND 8 and 10 elements

The zero output of the trigger 6 of channel 1 closes (blocks) the elements And 12 of the subsequent channels 2 and .3 and the element And 17. Next, the positive pulse of phase F is fed to the input of the element

trigger 5, which, as can be seen from the timing diagram shown in figure 2, does not affect the performance of the device as a whole, i.e. does not cause false locks of the And 11 elements of the subsequent channels and the And 18 element. Thus, the device is not critical, to the duration of the request signal, fulfills its function of priority selection by striking out the positive or negative phase clock pulse

synchronicity, and the time of selection is always less than the period of synchronization.

Claims (1)

Invention Formula Multichannel device for priority selection of pulses containing the element NOT, two elements of AND and n channels (n is the number of requests), and in each channel there are three triggers, 35 And 12 of the first channel, the pulse of sync .i 25 is the six elements AND, the element OR and phase F phase from the output of the element AND 12 through the element 14 enters the output 22 of the device and the single input of the trigger 4 of the first channel. Trigger 4 blocks AND 8 and 10 elements and prepares AND 7 and 9 elements for opening. A phase F sync pulse from the output of the AND 9 element sets the trigger 6 to the initial zero state, unlocking the And 12 and 17 elements occurs, and the output of the HE element 15 (through the element OR 13) high potential appears, which is set-. triggers trigger 4 to its original zero state. This case of the device is considered with the minimum duration of the request signal (Fig. 2, point a) arriving at input 19. The operability of the device at the maximum (unlimited) duration of the interrogation signal (Fig. 2, point b) arriving at input 19 does not differ from that indicated, with the only difference: the trigger 4 of channel 1 is reset to the initial state at the end of the interrogation signal arriving at input 19 and not upon completion of setting trigger 6 to the initial zero state (Fig. 2, point a). Naturally, due to delays in the operation of logic elements included in channel 1, it is possible (and existent) the so-called idle the element is NOT, the i-th input, where i 1, ..., (p-1), of the first element is connected to the inverse output of the first trigger of the i-ro channel and with the i-th input 30 mi first elements And from (i + 1) -ro of the n-th channel, n-th input of the first element I is connected to the inverse output of the third trigger of the n-th channel, (n + 1) -th input of the first element I from dinen with the first inputs of the second and third elements AND all channels with the corresponding inputs of the first elements AND of all channels and with the output of the element NOT whose input is connected 40 with a clock input of the device, the output of the first trigger of each channel is connected to the corresponding to the first element of the channel AND, the i-th input of the second element AND is connected 45 inverse output of the second trigger of the i-ro channel and the i-th inputs of the four elements And with (i + 1) -ro on the n-th channel, the n-th input of the second element And dinen with the inverse output of the second The 5Q trigger of the nth channel, (n + 1) -th input of the second element I is connected to the corresponding inputs of the fourth elements AND of all channels, with the first inputs of the fifth and sixth elements AND 55 of each channel and the clock input of the device, the direct output of the second three-channel of each channel is connected to the corresponding input of the fourth element AND of the channel, and in each channel you 35 25 six elements And, element OR, and the element is NOT, the i-th input, where i 1, ..., (n-1), of the first element I is connected with the inverse output of the first trigger of the i-ro channel and with the i-th input of the first elements I with (i + 1) -ro on the n-th channel, the n-th input of the first element And is connected to the inverse output of the third trigger of the n-th channel, (n + 1) -th input of the first element And is connected to the first inputs of the second and third elements And all channels , with the corresponding inputs of the first elements AND of all channels and with the output of the element NOT, whose input is connected 40 with a clock input of the device, the direct output of the first trigger of each channel is connected to the corresponding input of the first element AND of the channel, the i-th input of the second element AND is connected to 45 inverse output of the second flip-flop of the i-ro channel and i-th inputs of quarter I elements with (i + 1) -ro on the n-th channel, nth input of the second element And connected to the inverse output of the second 5Q trigger of the nth channel, (n + 1) -th input of the second element I is connected to the corresponding inputs of the fourth elements AND of all channels, with the first inputs of the fifth and sixth elements AND 55 of each channel and the clock input of the device, the direct output of the second trigger of each channel is connected to the corresponding input of the fourth element of the AND channel, and in each channel you are 5146 The inputs of the second and third elements And are connected respectively to the inverse and direct inputs of the second trigger, the outputs of the fifth and sixth elements And are connected respectively to the inverse and direct inputs of the first trigger, the outputs of the first and sixth elements And are connected respectively to the first and second inputs of the first the OR element, the output of which is the information output of the device and connected to the direct input of the third flip-flop, the outputs of the first and second elements AND of the device are respectively the first and second clock-outs and devices, the second inputs of the third and sixth elements And are connected to the inverse output of the third sixteen trigger, the direct output of which is connected to the second inputs of the second and fifth AND elements, characterized in that, in order to reduce the amount of equipment, it additionally contains a second OR element in each channel, and the device's request input is connected to the first input of the second OR element, the second and third inputs of which are connected respectively to the direct outputs of the first and second triggers, the output of the second element OR is connected to the input of the element NOT and to the third inputs of the third and sixth elements AND, the output of the element NOT each channel connected to the inverted input of the third flip-flop channel. g; five 16 19 13 Yu b 6 2nd tf S five 5 7 T | G1 TO w ////// J: Gz a-r iw Lz T | G1 TO w ////// mm (m. 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