RU1824632C - Device for information input - Google Patents

Abstract

The invention relates to the field of computer engineering, in particular, for inputting images from thermal imagers, televisions, and similar devices into a computer. also recording information highlighted by a programmable window within the frame. The input device contains two comparators, a pulse generator, element and line counts, a frame duration trigger, a coincidence circuit, a single-shot, a sampling and storage unit, and an analog-to-digital converter. The goal is achieved by gem, “then three programmable frequency dividers are added to the device, a frame duration trigger in window mode, two programmable delay elements, two multiplexers, a line length trigger, a line length trigger in window mode, two match patterns, four single vibrators, a control register and conditions. 3 ill.

Description

The invention relates to computer technology, in particular, for inputting a sequence of line-scan images into a computer, for example, information from tagging cameras, televisions, and the like.

The aim of the invention is to expand the scope of the device by providing software for the repetition rate of elements, the format of the recorded frames and the number of frames skipped, registration in the memory of the part of the frame highlighted by the window, the size and position of which in the frame is set by the operator when registering the sequence of images.

On Fig, 1 presents a block diagram of a device; Fig. 2h, b is a diagram explaining the operation of the device in the skip mode of a frame, line, and element; Fig. Za.b is the same in window selection mode.

The device contains two comparators 1.2, a pulse generator 3, a register of 4 states and controls, three programmable frequency dividers 5, b, 7, two multiplexers 8, 9, two programmable delay elements 10, 11, a trigger for line duration 12, a trigger 13 for line length in window mode, line counter 14, trigger 15 of the frame duration, trigger 16 of frame duration in window mode, counter of elements 17, five one-shots 18-21, 25 of the same circuit 00

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22, 23, 24, a sampling and storage unit (UHV), an analog-to-digital converter (ADC) 27.

Multiplexers 8, 9 are programmatically installed as follows. that the SSI from block 5 passes to the input of the trigger of the CSI, from block 6 passes to the input of the trigger 15. The delay circuits 10, 11 can be programmed to delay any number, since the generated frame and line durations are determined by the sum of the delay operation time and counter of lines (elements). Upon receipt of a frame clock (CSI) from block 6, trigger 16 enters the log state. 1 synchronously with the first horizontal sync pulse (SSI) coming from block 5. and trigger 15 is transferred to the state of the CSI directly. The SIDs from block 5 go to the inputs of the delay circuit 10 and the line counter 14. The permission to count the number of delay lines (block 10) is received from the trigger 16, and the resolution to the counter 14 is issued by the block 10 after calculating the specified number of the SSS delay. The counter of the number of lines 14 will calculate the number of lines equal to the difference between the number of lines specified by the external device and the number of delay lines. For convenience, in full frame mode, you can set the number of delay lines equal to the minimum value for timer 2.

At the end of the count of the total number of lines K in the frame, the counter 14 through the one-shot 19 resets the triggers 15, 10, bringing them back to their original state. Thus, at the output of the match circuit 23, the inputs of which are connected to the outputs of the triggers 15, 16, a pulse of the frame duration of the DC 23 of the duration of the C lines is generated. A pulse of the duration of the DC 22 line is generated similarly. After the arrival of the SSI, the trigger 12 (TBS12) is transferred to the logical state 1L synchronously with the 1st sync pulse of the element coming from the second output of block 7. Trigger 13 is transferred to state 1 directly by the SSI passing through the multiplexer 8. The clock pulses of the elements (SC) from block 7 are fed to the inputs of the delay circuit 11 and the counter Single 17. When a resolution of the row latch delay circuit 12 calculates a predetermined number of elements and authorizes the operation of the counter 17, counter 17, having counted the total number of elements in the line C through the monostable 20 causes the triggers 12, 13 in the initial state. Thus, at the output of the coincidence circuit 22. The inputs of which are connected to the outputs of the triggers 12,13, a pulse of the duration of the string DC 22 with the duration of C elements is generated. Upon arrival of the Start command, synchronized

with the CSI. Pulses of Start, DK23, DS22 and SE are received at the input of the coincidence circuit. If Start, DK23, DS22 coincides, the clock pulses of the elements pass to the output of the circuit

24. In this case, the frame contains K lines and C elements in each line, the number of which is determined by an external device and is programmatically recorded in line and element counters.

0 In FIG. 3, an example diagram is shown in window mode. In this mode, through the control inputs from the control and state register 4, the second junctions of the frame mode selection multiplexers 9 and 9 are turned on.

5 rows are 8, and delay blocks are 10. 11, counters 14, 17 are programmed in the following modes: delay block of the number of lines 10 ne K3 lines, counter of the number of lines in frame 14 per KST of lines (Kz + KSt - K. where K is the maximum a certain number of lines and a frame, determined by the type of external device and the number of punctured lines, a block of delay of elements 11 in C.-) elements, a counter of the number of elements in line 17 on Cell elements.

5 moreover, Ca + Сel С, where С is the maximum number of elements per line, taking into account the element reduction).

When the CSI arrives from block 6, trigger 16 synchronously with the line pulse switches to logical state 1. CTOOI delay circuit: 10 calculates the delayed number of lines C and then gives permission to the counter of the number of lines 14 and simultaneously through the single-shot 18,

5, the second input of the multiplexer 9 brings the tripper 15 (TDK015) to state 1. At the end of the counting of the number of lines Kc, the counter 14 is through a single-fiber; ior 19 returns the triggers 15, 16 to the initial state. Outputs

0 triggers 15, 16 go to the input of the match circuit 23. At the output of the CXPMA match 23 (), a window duration pulse is generated in the DK23 frame, which coincides with the TDK015. In each frame, n

In window mode 5, a DC23 pulse is generated with the duration of the Ket lines delayed by K3 lines relative to the start of the frame.

Window formation in rows is done in a similar manner.

0 When the SSI arrives from block 5 (SSI 5), the line duration trigger 12 goes to logic 1 synchronously with the arrival of the first C3i from block 7. The element delay circuit 11 calculates the delayed number of C3 elements and then gives permission to operate the counter of the number of elements in the line 17 and simultaneously through the one-shot 21 and the multiplexer puts the trigger 13 in state 1. At the end of the count of the number of elements in

In the SEP line, the counter 17 returns the triggers 12 through the one-shot 20 to the initial state. The outputs of the triggers 12, 13 are fed to the inputs of the matching circuit 22. At the output of the matching circuit 22 (DS23), a window duration pulse is generated in the string DC23, which coincides with TDS013. Thus, in each line in window mode, a pulse of DS 23 is formed with a duration of Ce elements delayed by С3 relative to the beginning of the line.

When the Start command is received from an external source (computer, button, pulses) at the start input, synchronous 1 is set to logic 1 and, if the elements coincide, the clock pulses of the elements (SE 7) are passed to the output of the matching circuit 24. Thus, the synchronizing pulses are transmitted to the output of the matching circuit elements C3i, arriving only in a window the size of Kc lines on Ce elements, shifted relative to the beginning by K3 lines on top and C3 elements on the left.

In the skip mode of frames, lines and elements, blocks 5, b are programmed. 7, which skip a given number of frames, lines and elements of the corresponding blocks (indicated by numbers) in the skip mode of one frame, line and element in a line. The figure shows the CSI. SSI, C, E - clock pulses of frames, lines, and elements at the output of the drivers: KCHi, CC / l ;, C3i - clock pulses of frames, lines, and elements at the output of frequency dividers in a 1: 2 division mode; TDK, TDS - pulses at the output of triggers for the duration of the frame and lines.

In Fig. For the pre-presentation diagram of the operation of the device in the mode of selecting a window and skipping one frame, line and element. As in Fig. 2, the block numbers are indicated and the designations are entered: SSI2, SEa - pulses at the output of programmable delay circuits of lines (10) and elements (11); IZNK, IHKK, IZNS, IZKS - impulses of delay in the beginning and end of frames and lines in the TDKO window mode; TDSO - pulses at the output of the trigger duration of frames (15) and lines (13) in window mode; DK, DS - pulses of the duration of the frame and lines generated in window mode.

On Fig shows the pulses received at the input of the matching circuit 24, and the output pulses received at the input of a single-shot 25.

The device operates in two modes:

1. The skipping mode of elements, lines and frames defined by software from a computer.

2. In addition to the first, the selection of any part of the frame by the window and information registers inserted by this window is specified.

Consider the operation of the device in the first mode. At the same time, on the multiplayer mountains, by choosing the mode of frame 9 and line 8, through the control inputs from the control register and states 4, the first inputs are connected to which the clock pulses of the lines (SSI), frames (CSI) and

0 elements (SE).

Begin sync pulses (CSI). coming from an external device are formed by a comparator 2 and divided by a frequency divider 6 in a ratio defined

5 programmatically from a computer through the register controlled and state 4, providing a pass during registration of a given number of frames. From the output of frequency divider 6, the frame start pulse goes directly to trig0 rep of frame duration 16 and through the first input of multiplexer 9 to the frame duration trigger in window mode 15. At the same time, they are transferred to the log state. 1, which is fed to the first input of the 4-input circuit

5 matches 24. Signal log. 1 from the output of the trigger 16 starts the delay circuit 10, which is programmed in such a way that immediately allows the counting of pulse pulses to the counter 14. Return triggers 15, 16

0 to the initial state is produced by the pulse of the end of the line counting in the frame from the line counter 14 through the single-shot 19. Thus, the duration of the recorded frame at the first input 45 of the input coincidence circuit is set to resolution 1 h level (log T).

Syn, line pulses (SSI) coming from an external device are formed by comparator 1, divided by a divider

0 of frequency 5 in a ratio adapted from the computer programmatically through the control and state register 4, providing thinning (skipping) when registering a given number of lines. From the output of the divider 5 bodies of frequency 5, the pulse of the beginning of the line goes directly to the trigger line 12 of the line duration and through the first input of the multiplexer 8 to the input of the line length trigger 13 in window mode, at the same time, they are logged to state 1. At the same time, at the output of the matching circuit 22, a resolving level (log. 1) appears, which nocrynaei goes to the second input of the 4-input matching circuit 24. The signal log. 1 from the output of trigger 12 triggers a delay element 11, which is programmed so that immediately does not allow the count of impulses of elements to the estimator 17. The triggers 12 13 are returned to their initial state and the corresponding snupstop - ag, p-: hl on the basis of the input of the matching circuit 24 is produced by the pulse of the termination of the counting of elements in the line by the element counter 17 through a single vibrator 20. Thus way for dl the logged line on the second pass of the 4-input match circuit is set to logical 1st (Fig. 2, diagrams 4-6 in the single line skip mode). For synchronization of frames and lines, the SID from the output of the comparator 2 is fed to the third input of the frame duration trigger.

The pulses from the pulse generator 3 are divided by a frequency divider 7 in the ratio set from the computer through the control register and state 4, and the division coefficient is determined both by the type of thermal imager (differing in the speed of the frame-scan and spatial resolution), and the selected number of elements in the line (sparse skipped elements). Pulses of the element clock (SE) from the output of the frequency divider 7 go to the third input of the 4-input match circuit 24, to the first input of the programmable delay circuit 11, the first input of the element count 17. In the memory of which the number of elements in the line is written from the computer control and status register 4.

At the end of the counting of the elements, the output pulse of the counter 17 launches a new Orator 20, the output pulse of which resets (leads to the initial state) the trigger for the duration of the line 12 and the trigger for the duration of the line s in window mode 13, which, in turn, set the prohibition through coincidence circuit 22 (logical O) at the first input of the 4-input match circuit 24 (FIG. 2, diagrams 7-10 in the single element skip mode). In order to synchronize the operation of the trigger of the duration of line 12 with the elements, FE is supplied to its third input from the second output of the divider 7 (maximum frequency for each type of thermal imager).

Thus, in the first mode (without a window), the following pulses are received at the inputs of a 4-input match circuit (Fig. 2): at the first input, a frame duration pulse that sets the log, 1 during the duration of only selected frames; to the second input, an impulse of line duration that sets the log. 1 for the duration of the selected rows; to the third input, read pulses of elements with a given frequency, arriving continuously; on the fourth - the Start pulse coming from a computer, an operator or an external device, and the Start command synchronizes with the start pulse of the frame. After coming

Start commands and the presence of pulses of the duration of the frame and the lines of the read pulses of the elements pass through the match circuit 24, start the one-shot 25,

which produces pulses that transfer the UVX 26 to the storage mode, and with a delay determined by the speed of the UVX, the ADC start-up pulses 27. At the end of the conversion, the ADC outputs a digital

0 information to information outputs in a computer or memory block in which a sequence of frames of a given format (the number of lines and frame elements) is stored. Information is recorded by pulse 5. The end of the conversion from the ADC to the control output.

Setting the division factors (skipping) of line dividers 5, G frames, elements 7, as well as setting the number

0 lines in the frame in the line counter 14 and the number of elements n line D element counter 17 is produced from the computer via the interface using the control register 4 and the state

Research institutes.

5 The first mode allows you to change the format of the code and restrict it to the bottom and the left by programmatically setting the number of recorded lines in counter 14 and the number of elements in line counter 17 is less than their

0 maximum number after dividing by frequency dividers 5 and 7,

Consider the operation of the device in the second mode - window mode, that is, registration of any selected software part of cad5 ra. At the same time, on the multiplexers for selecting the frame mode 9 and line 8, the second inputs are switched on via the control inputs from the control register 4.

The restriction of the window from the top and the bottom is set by program input from the computer through the control register and states 4 of the number of delayed lines to the delay element, 10 and the number of lines in the window to the line counter 14. Window restriction to the left and right

5 is set by program input from a computer through the control register and states 4 of the number of delayed elements to the delay element 11 and the number of elements along the window width to the element counter 17.

0In contrast to the first mode, pulses

at the output of the delay element 10, they are delayed by a predetermined number of lines relative to the frame start pulse coming from the frame duration trigger 16. The delayed 5th pulse from the output of the delay circuit is fed to the control input of the line counter 14, allowing the SSI to be counted and simultaneously through the single-vibrator 18 and the 2nd input of the multiplexer 9 is fed to the input of the duration of the frame frame about window mode 15. On

the inputs of the matching circuit 23 receive pulses of the duration of the entire frame from the trigger 16 and selected by the window from the trigger 15, From the output of the matching circuit there are pulses allocated in rows by the window from the trigger 15, which is fed to the input of the 4-input matching circuit 24 (fz.Zz , diagrams 16, 15, 23 in the skip mode (through) one line and limited by a window from 3 to the penultimate line).

As programmable de / n-gels of frequency 5, 6, Tc counter 14, 17, npoi of ramp delay elements 10, And programmable interval timers of the КР580 series can be used.

Triggers 12, 16 can be performed in a two-stage scheme. The first stage is set asynchronously (trigger 12 according to FID, trigger 16 according to FID), the second stage is rewritten the state of the first step according to sync signals FID and SC (trigger 12 by FEC, trigger 16 by FID). PS can be used as three herpes of frame duration 15 and line 13 in window mode.

The Start command of the device is formed synchronously with the start of the kag.ra. The formation circuit can be executed, for example (in FS.1 it is not shown on the coincidence circuit on the outputs of which a start pulse from the computer and a start pulse from the output of the frame divider 6 are fed. If these pulses coincide, the signal from the output of the coincidence circuit turns the trigger over, the output which gives permission for the 4th input of the matching circuit 24, allowing the passage of pulses of the start of the IWC and the LCP. The reset of the trigger and the stop of the operation of the IWC and the LCP is made by the pulse. The end of the record coming, for example, from the memory unit.

Such a solution of the device makes it possible to register all frames of the order during fast-flowing processes and to ensure the passage of 1, 2, 3 ... frames during slow-running processes, making optimum use of the memory in which the registration is made.

Changing the frame format makes it possible to optimize the recording resolution depending on the type of process. If small details of interest to the operator are observed in the frame, then full-format frames are recorded. If there are no such details, then the frame size can be reduced by thinning out the lines of elements in a line or by reducing the number of lines and elements at the same time. At the same time, the number of frames recorded in the memory of the uproot is simultaneously increased. For example, registering a frame ф,: рм: п 50x50 instead of 100x100, allows to increase the number of frames registered in the memory by 4 times. This is especially important when registering 5 lengthy processes. Similar benefits; it has the ability to register information highlighted by the window within the frame.

Claims (1)

The claims 0 A device for inputting information, containing the first and second comparators, the inputs of which are connected to the outputs of the solid and frame sync pulses of the device, a pulse generator, counter 5 elements, a line counter, a frame duration trigger, a coincidence circuit, a single vibrator, the outputs of which are connected to the control inputs of a series-connected sampling and storage unit and 0 analog-to-digital converter, the input of the sampling and storage unit is connected to the video signal output of an external device and is the information input of the device, and the output of the analog-to-digital converter is the information output of the device, characterized in that, in order to expand the scope of application, it additionally three frequency divider programs, a frame length trigger in window mode, two programmable delay elements, two multiplexers, a line length trigger, a line length trigger in window press, two match patterns, four 5 additional single vibrators and a control and status register, the information inputs of which are the control inputs of the device, and the digital outputs are connected to the installation inputs of programmable frequency dividers, programmable delay elements, element and line counts, control inputs of the first and second multiplexers , the output of the first comparator is connected to the first 5 by the input of the trigger of the duration of the frame and with the counting input of the first programmable frequency divider, the output of which is connected to the first input of the trigger of the duration of the line, the first information input 0 of the first multiplexer, with a counting input of a line counter and a counting input of the first programmable delay element, the control input of which is connected to the output of a trigger of duration kpdrl, and output 5 with a control counting input of a line counter and through psr-i an additional one-vibrator with ОРМ шпппппм the house of the second multiplexer, the output of which is connected to the r-th-t-stroke of the t-trigger of the feces duration; 1-th-th of the second output of the last bit of the line counter through the second additional single-shot is connected to the second inputs of the trigger and the duration of the frame and the trigger for the duration of the frame in window mode, the outputs of which are connected to the corresponding inputs of the first coincidence circuit, the output of which is connected to the first of the inputs of the second coincidence circuit, the output of the second comparator via the second programmable frequency divider is connected to the second input of the trigger for the duration of the frame and to the second information input of the second multiplexer, the output of the pulse generator is connected to the counting input of the third programmable frequency divider, the first output of which is connected to the second trigger stroke line width, and the second output - to a second input of the second coincidence circuit and to the count input of the counter element and the second programmable delay element, control inputs of which is connected to the output of the trigger line duration, and the output - to the control of the account the input of the counter of the elements and through the third additional one-shot - to the second information input of the first multiplexer, the output of which is connected to the first input of the line duration trigger in window mode, the output of the last bit of the element counter through the fourth additional single-shot is connected to the second inputs a string duration trigger and a string duration trigger in window mode, the outputs of which are connected to the corresponding inputs of the third match circuit, the output of which is connected to the third input of the second The coincidence circuit, the output of which is connected to the input of the one-shot, the output The conversion end of the analog-to-digital converter is the control output of the device, and the fourth input of the second circuit coincidence is the control input of the Start device, and the counters of elements and lines are made programmable. FIG. 2 5 B KCU TDK16 TDK015 ecus TLS11 S3.1 GLS013 J v v XjC / npOX Xf C / 77Ј 0 / f Lc / rtpoxa LUSK DKGZ Chipboard Fig j j v sz L. Rows