SU1672586A1 - Synchronous generator - Google Patents

Abstract

The invention relates to television technology and can be used in synchronization devices for television systems and automated image processing systems. The purpose of the invention is to enhance the functionality by providing external synchronization. The synchronous generator contains the master oscillator 1, the first counter 2, the first permanent memory unit 3, the first buffer register 4, the second counter 5, the second permanent memory unit 6, the second buffer register 7, trigger 8. The goal is achieved by introducing a frequency divider 9, shaper 10 of the synchronization signal, the first and second one-shot 11, 12, the first and second elements And 13, 14, the first and second blocks 15, 16 of the task code. 3 il.

Description

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The invention relates to television technology and can be used in synchronization devices for television systems and automated image processing systems.

The purpose of the invention is to enhance the functionality by providing external synchronization.

Figure 1 shows the structural electrical circuit of the synchro generator; FIGS. 2 and 3 are timing diagrams explaining the operation of the sync generator.

The synchronous generator contains the master oscillator 1, the first counter 2, the first permanent memory unit 3, the first buffer register 4, the second counter 5, the second permanent memory unit 6, the second buffer register 7, the trigger 8, the frequency divider 9, the signal conditioner 10 synchronization, the first 11 and second 12 single vibrators, the first 13 and second 14 elements I. the first 15 and second 16 blocks of the task code.

Sync generator works as follows.

A master oscillator 1 with quartz frequency stabilization generates rectangular-shaped pulses with a frequency of, for example, 25 MHz. These pulses are fed to the counting input of the splitter 9 frequency. In the case of a master oscillator frequency of 25 MHz, the frequency divider factor of 9 is equal to 4 and can be made in the form of serially connected two counting triggers with a reset. From the output of divider 9 frequency, square-shaped pulses with a frequency of 6.25 MHz arrive at the counting input of the nine-bit first counter 2, the discharge outputs of the first counter 2 are connected to the address inputs of the first permanent memory unit 3. The binary nine-bit code on the bit outputs of the first counter 2 is the address code for the first permanent memory unit 3 having a structure, for example. 512x8 bits and made on the basis of a programmable read-only memory (PROM) with a sampling time of no more than 80 not. In the first block 3 of the permanent memory, at the programming stage of the EPROM, information is flashed to ensure that the following pulse signals are formed at the output of the block: address of the block of the horizontal frequency (FIG. 2a), horizontal sync pulses (FIG. 26), horizontal lowering pulses equalizing pulses (Fig. 2c), frame sync group pulses (side bars, Fig. 2d), reset pulses of the second counter 2. The remaining two bits of the EPROM can be used to generate additional signals. The signals generated at the output of the first block 3 of the permanent memory are fed to the information inputs of the first buffer register 4.

The need to use the register

due to the following circumstances. EPROM address signal decoders may have some variation in response time. As a result, the outputs

0 of block 4 of persistent memory, pulsed interferences of a few nanoseconds duration may occur. To eliminate these interferences, strobe output is recommended. Signals

5 formed at the outputs of the first block 3 of the permanent memory are gated with a positive difference of pulses from the output of the frequency divider 9 at the synchronization of the back buffer register 4. At the outputs of the first buffer register 4, the information has the same purpose as at the inputs.

Thus, the output of the first buffer register 4 contains signals

5 line frequency listed in Table 1.

The reset pulse of the first counter 2 determines the period of the 64 µs row and yccAn this counter in O. When using the master oscillator 1 with a frequency of 25 MHz

0 and the divider 9 frequency per 4 period of the pulses arriving at the counting input of the first counter 2. is not 160 Therefore, during the horizontal period of 64 µs, this counter should calculate 400 periods of the frequency arriving at its input. This is ensured by the fact that the third bit of the EPROM at address 399y is recorded at the programming stage 1. The counter sequentially forms a binary code, starting from zero. the moment when the binary code at the address inputs of the first block 3 of the permanent memory corresponds to the cell address 399yu, in the third bit, the EPROM is read out 1. the torus is fed to the third information input of the first buffer register 4 and passes after gating to its third output, from which It is applied to the reset reset of the first counter 2. On arrival 1 at the input

0, the first counter 2 is set to O, a zero code is formed on the bit outputs of the counter, which is the address code for the first permanent memory unit 3. Next, the pulses coming

5 to the counter input of the counter, provide a sequential search of the addresses of the permanent memory to the address corresponding to the cell number 399, and the counter is reset again. In this way, the counting cycle of the first counter, which

is 400 periods of pulses passing to its counting input and is equal to a row period of 64 µs.

The bit outputs of the first counter 2, which are the fifth output of the device, can be used to address elements per line in automated image processing systems.

In the case when the synchronous generator is used in the external synchronization mode, external horizontal sync pulses are applied to the input of the first one-oscillator 11, which is the first input of the synchronous generator. On the leading edge of the horizontal sync pulse, the one-shot 11 produces a pulse with a duration of 200 ns, which resets the frequency divider 9 to O and is fed to the preset input of the first counter 2. This pulse causes the counter to be set to the state determined by the code from the first block 15 assignments of the code to the information inputs of the first counter 2. Moreover, the taxi is supplied with a binary code that corresponds to the beginning of the formation of the horizontal sync pulse in the first discharge of the EPROM of the first block 3 constantly memory.

Thus, phase matching of the horizontal sync pulses generated by the synchro generator and external sync pulses fed to the first input of the device is realized.

The horizontal sync pulses from the output of the first block of 3 permanent memory are fed through the first buffer register 4 to the counting input of the second counter 5. This counter is a nine-bit binary counter with reset, preset, and information inputs. The first 2 and second 5 counters in the sync generator are identical. The second counter 5 counts the number of lowercase clock pulses arriving at its counting input. From the first to the sixth, the bit outputs of this counter are connected respectively to the inputs of the second to seventh address inputs of the second block 6 of the permanent memory. At the input of the first address bit (lower address bit) enters the meander of the horizontal frequency. This provides for the reading of information from the second constant-memory unit 6 with a double line frequency, which is necessary for the correct formation of frame-rate signals received for interlaced scanning. The output of the older ninth bit of the second counter is connected to the ninth inversion input (chip select) of the second block 6 of the permanent memory and to the counting input of the trigger,

the output signal of which determines the number of the half-frame (O - in the first half-frame, 1 - in the second half-frame) of interlaced scanning. This signal from the output of trigger 5 is supplied to the ninth information input (low-order) of the second counter B and to the input (eighth) of the high-order address bit of the second permanent memory unit 6.

The second block 6 of the permanent memory has 10 structure, for example, 256x4 bits and is made on the basis of an EPROM with sampling times of no more than 80 not. The address space of this block is divided into two pages of 128x4 bits, which are switched by the highest address bit — 15th house (entry 8). In the first half-frame, information is read from the first page (on the high address bit de O), in the second - from the second page (on the high address bit 1), Necessity

0 the use of the paging organization of the second block 6 of the permanent memory is due to the fact that the frame frequency signals with interlaced scanning formed in this block have a different time position relative to the horizontal sync pulses. In each of the two pages of the second block 6 of the permanent memory, at the programming stage, information is stitched to ensure that the following pulse signals are generated at the output of the block: frame sync pulses, frame damping pulses, and reset pulses of the second counter 5, frame switching pulses

5 sync groups. The signals generated at the output of the second block 6 of the permanent memory are received at the information inputs of the second buffer register 7, the purpose and principle of operation of which are similar to the first buffer register 4.

Thus, at the outputs of the second buffer register there are signals of the frame frequency (Table 2).

Starting from the zero state, the second

5, the counter 5 counts the number of horizontal sync pulses arriving at its counting input (FIG. 26). During the arrival of the first 256 pulses, which corresponds to the first 256 lines, the highest ninth bit of this counter is in the state O. Since the ninth bit output is connected to the access input (input 9) of the second fixed memory block, this corresponds to the absence of a reference signal. With

5, the arrival of the next horizontal sync pulse, the output of the higher bit of the second counter 5 goes to state 1 (FIG. 2e, k), and the information starts to be read out from the second permanent memory unit 6. The information is read by

sequential search of addresses at the inputs of the first to eighth address bits of the block. Moreover, a horizontal frequency meander is fed to the input of the first (lower) address bit, which ensures that the PROM of the second block 6 of the permanent memory is polled to 32 µs (0.5 horizontal period). This is necessary for the correct generation of frame frequency synchronization pulses having a different temporal position in the first and second half-frames (with an accuracy of 0.5 line period). The output of the ninth (most significant) second counter 5 is connected to the counting input of the trigger 8. The trigger 8 is a T-trigger and performs the function of dividing the frequency by two. With the arrival at the counting input of the second counter 5 of the 257th row sync pulse, the senior (ninth) counter of the counter goes to state 1, which means that the information from the second permanent memory unit 6 is read. At the same time, a positive differential of this signal, arriving at the counting input of the trigger 8, switches the trigger output to the state O (suppose that the previous state is 1). The output of the trigger 8 is the seventh output of the clock generator and can be streamed as an indication of a half frame.

At the same time, the signal from the output of the trigger 8 is fed to the input of the eighth (senior) address bit of the second block 6 of the permanent memory and determines the page number (O or 1) from which the information is read. In the first half-frame (page 0), a reset pulse is read from 56 second periods (Fig. 2e) from the second permanent memory unit 6 (output 3), which through the second buffer register 7 (output 3) is fed to the reset input of the second counter 5. Thus, the counting cycle of the second counter 5 in the first half-frame is 256x56 312 string periods. The reset pulse sets all bits of the second counter 5 to O, therefore, the reading of information from the second block 6 of the permanent memory is stopped. Next, the next counting cycle (second half frame) begins. Similarly to the previous one, the first 256 line periods of information from the permanent memory block are not read. The 257th horizontal sync pulse translates the ninth (senior) digit of the second counter 5 into state 1 (Fig. 2k), which corresponds to the resolution of reading information from the second permanent memory unit 6. A positive differential at the ninth output of the counter transfers the trigger 8 to the state G (the previous state O). Log, 1 from the output of the trigger 8 enters the most senior (eighth) address input of the second 6 blocks of the permanent memory, which determines the reading of information in the second half-frame from its second page. Through 57 lowercase

drops (Fig. 2) in the second half-frame from the second permanent memory unit 6 (output 3) reads a reset pulse, which through the second buffer register 7 (output 3) is fed to the reset input of the second counter 5.

0 Thus, the counting cycle of the second counter 5 in the second half-frame is 256 + +57 313 string periods. The reset pulse resets the counter 5, and the reading of information from the second block 6 stops.

5 permanent memory. The appeal to the second block 6 of the permanent memory during a single frame is made in 57 + 57 113 lowercase periods from 625.

The bit outputs of the second counter 5

0 can be used to address elements vertically in automated image processing systems and are the sixth output of a sync generator. In the case when the sync generator is used in the external synchronization mode, external personnel sync pulses are supplied to the input of the second one-shot 12, which is the second input of the synchro-generator (Fig. 3a). On the front edge

0 frame sync pulse the second one-shot 12 forms a pulse (FIG. 36) with a duration of no more than half of the line period, for example, 20 μs. This impulse goes to the first input of the second element.

5 And, to the second input of which equalizing pulses arrive (Fig. 3b) with a period of the next 32 µs. As a result, a pulse is formed at the output of the second element I 13 (Fig. 3d). corresponding to the beginning of the block. This pulse is applied to the input of the preset of the second counter 5 and to the second input of the second element I 14, to the first input of which the horizontal sync pulses (FIG. 3) are fed from the first output of the first buffer register 4. As a result, the output of the second element 14 at the beginning of the first The half frame is formed by the preset impulse, which is fed to the preset input in the On trigger 8, Trigger 8

0, this is set to O. Thus, at the beginning of the first half-frame of interlaced sweep, trigger 8 is set to O, and during this half-frame to the senior address input of the second permanent memory unit 6, which determines the switching of one of its two pages, O is supplied. In addition, from the output of the trigger 8 log. O is supplied in the first half frame to the ninth (junior bit) information input of the second counter 5. In

to the second half-frame, the beginning of the frame sync pulse does not correspond to the beginning of the line sync pulse, and the pulse of the preset (Fig. Ze) at the output of the second element I 14 is not generated. By the beginning of the second half-frame, the trigger 8 is transferred to the state 1 by the output signal of the ninth (senior) bit. Therefore, during reading the information from the second block of the 6th permanent memory, its second page and the ninth information input (low-order) are turned on The second counter 5 is supplied G. The impulse of the preset generated by the first element I 13 initiates, at the beginning of the first half-frame, the installation of the second counter 5 in the state 100000110 (low order O, the code on the outputs of the second block 16, setting the code 10000011) to the beginning of the second half ra - to the state 100000111 (the least significant bit 1, the code at the outputs of the second block 16 of the task code 10000011).

The synchronization signal generator 10 performs the function of generating a receiver synchronization signal (SSP), which from the output of the generator 10 enters the eighth output of the clock generator (Fig. 2i, o). While no pulses are generated at the outputs 1 and 4 of the second buffer register 7 (Fig. 2g, m, 3, n), the horizontal sync pulses from its third input are output to the output of the shaper 10. At that time, when the fourth output of the second buffer register 7 and, accordingly, at the fourth (control) input of the driver 10, a switching pulse of the frame sync group is formed (Fig. 2g, m), and the frame clock (input 5 of the driver 10) is not formed, equalizing pulses are commuted from the second input to the output of the former 10. While the frame sync switching pulses and frame sync pulses are generated at the same time, the inset pulses from the first input are switched to the output of the imaging unit 10.

Claims (1)

Invention Formula A synchronous generator containing a master oscillator, serially connected first counter, block of permanent memory and first buffer register, the first and second outputs of which are respectively the first and second outputs of the synchronous generator, as well as a trigger and serially connected second counter, second block memory and the second buffer register, the first and second the outputs of which are respectively the third and fourth outputs of the clock generator. characterized in that, in order to expand the functional possibilities by providing external synchronization, the first and second single vibrators, the first and second And elements, the frequency divider, the synchronization signal generator, the first and second code setting blocks 10, the outputs of which are connected from the first via the eighth information inputs of the first and second counters, respectively, while the input of the first one-shot is the first input 5 of the clock generator. and the output of the first single-vibrator is connected to the preset input of the first counter and the reset input of the frequency divider, to the counting input of which the output of the master oscillator is connected, and output 0 of the frequency divider is connected to the input inputs of the first and second buffer registers and the counting input of the first counter, the reset input of which is connected to the third output of the first buffer register, the fourth, fifth, fifth and first outputs of which are connected to the first, second and third inputs of the synchronization signal generator, and the second input is one The selector is the second synchronizer return, and the output of the second one-oscillator is connected to the first input of the first element I, the second input of which is connected to the fifth output of the first buffer register, the first output of which is connected to the counting input of the second counter and , to the second input of which and the input of the preset of the second counter the output of the first element I is connected, and the output of the second element I is connected to the input of setting 0 of the trigger, to the counting input of which and the input of the second block constant The ninth output of the second counter is connected to the amy; the third output of the second buffer register is connected to the reset input; the fourth and first outputs of the second buffer are connected to the fourth and fifth inputs of the synchronization signal generator, and the sixth output of the first buffer register is connected to the input of the first address split 0 p of the second block of the permanent memory, to the input of the higher address bit of which and the nine information input of the second counter the output of the trigger is connected, and the bit outputs of the first counter, 5 outputs of the bit a second counter, the flip-flop output and the output synchronization signal shaper are respectively fifth, sixth, seventh and eighth output clock. Exit first buffer register 4 Signal description one Lowercase sync pulses Lower quenching pulses, optional information pulse reset first counter 2 Frame sync pulses (sidebars) Equalizing impulses Horizontal frequency meander Output second buffer register 7 Signal description Frame sync pulse (Fig. 2z, n) Frame damping pulses Impulse reset second counter 5 (fig. 2e, l) Switching impulse staffing sync group (Fig. 2g, m) Table 1 Where it goes The first output of the synchronizer, the third input of the generator 10 of the synchronization signal, the counting input of the second counter 5, the first input of the second element And 14 The second output of the synchronous generator Reset input first counter 2 The first input of the synchronizer signal 10 The second input of the synchronization signal generator 10, the second input of the first element AND 13 the input of the first address bit of the second block of 6 permanent memory table 2 Where it goes The third output of the clock generator, the fifth input of the driver 10 of the synchronization signal The fourth output of the clock generator The reset input of the second counter 5 The fourth input shaper 10 synchronization signal JLJL j-JLJL ijLJLJ JШUlJ 4LpJLL4USShSh jTinn i | ihTin | i} TTirfi r f | IT JLJLJJLMJUUTTITiri ii. .j JJLJLJL-JUUUULhnn n I ± JLLLOJJJUb (LlJJLLJlJL JL LJL JJJ PIL Jl n