SU1085006A1 - Cyclic phasing receiver - Google Patents

Abstract

A CYCLE PHASE RECEPTION DEVICE, containing sequentially connected a sync group decoder, an OR element, a first shift register and a predetermined state decoder, a cycle counter, the clock input of which is combined with the clock input of the first shift register and the clock input of the synchro group, and a tact clock of the synchro group and a tact clock of the synchrograph group and a clock signal of the synchro group, a clock loop, a clock loop, a clock input that is combined with a clock input of the first shift register and a clock input of the synchrograph group, a clock loop, a clock loop input, a clock loop input, and a clock signal, a clock loop, a clock loop, a clock loop, a clock loop, a clock loop, a clock input, a clock register, and a clock loop input, different in that, in order to improve noise immunity in the steady state, a trigger connected in series and a first AND element, a second AND element in series, a second shift register and a third And element, whose output is connected to the information input of the cycle counter, are entered into it, the output of the first shift register through the first element. And is connected to the second input of the OR element, the input of the decoder of a given state is connected to the first input of the trigger and the auxiliary input of the third element And, the output of the cycle counter is connected to the second input of the second shift register, the second input {of the trigger and the first input of the second el element And, the second the input of which is keyed to the output of the synchro decoder.

Description

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The invention relates to the field of transmitting digital information and can be used for cyclic phasing (synchronization trietrams in reliability enhancing devices, telegraphy, telemetry, image transmission, etc.

A frame alignment receiver is known, which contains a serially connected strobe block, a key block, a first OR circuit, a shift register, a first decoder, a combination counter and a phase pulse extraction unit connected in series by a second decoder, a block for changing the dividing period, and a frequency divider whose output is connected to the second input of a money block strobe, the second OR element and the control trigger, whose output is connected to the second input of the key block, are connected in series, This is connected to the first input of the multiplication element, the second input of which is combined with the second input of the control trigger and connected to the auxiliary output of the shift register, and the output of the multiplication element is connected to the second input of the first OR element and the second input of the phasing pulse extraction unit, the output of which is connected to the second input the second element OR and the second input of the shift register Cl.

The disadvantage of this frame alignment receiver is the large time to synchronization during the sequential analysis of the cycles and the low noise immunity when the synchronization signal is distorted by interference.

The closest technical solution to the invention is a cyclic phasing receiver comprising serially connected sync pattern decoder, OR element, first shift register and predetermined state decoder, cycle counter, the clock input of which is combined with the clock input of the first shift register and the clock input of the synchrogram decoder and is the clock input of the device, the output of the first shift register is connected to the second input of the OR element, and the output of the decoder of a given state is connected n to the reset input of the first shift register and the cycle counter C22.

A disadvantage of the known cyclic phasing receiver is that, in steady state, with a regular repetition of a false sync group at some position and a random distortion of the true sync group, the cycle counter can be set to a false phase, i.e. the frame alignment will fail, although true sync groups will arrive at a given cycle position. Thus, in the steady state, the known device has insufficient noise immunity.

The purpose of the invention is to improve the noise immunity in the steady state.

The goal is achieved in that a cyclic phasing receiver containing serially connected sync pattern decoder, an OR element, a first shift register and a predetermined state decoder, a cycle counter, the clock input of which is combined with the clock input of the first shift register and the clock input of the synchro group decoder and the clock input of the device, entered in series the trigger and the first element AND, the serially connected second element AND, the second shift register and the third ele And, the output of which is connected to the information input of the cycle counter, the output of the first shift register through the first element AND is connected to the second input of the OR element, the output of the decoder of a given state is connected to the first input of the trigger and the auxiliary input of the third element And, and the output of the cycle counter is connected to the second input of the second shift register, the second input of the trigger and the first; / the input of the second element And, the second input of which is connected to the output of the sync pattern decoder.

The drawing shows a structural-electrical circuit for receiving a cyclic phasing device.

The cyclic phasing receiver contains a sync pattern decoder 1, the element OR 2, the first shift register 3, the decoder 4 for the open state, the first element AND 5, the trigger b, the second and third elements And 7 and 8, the second shift register 9, the counter 10 cycles, informational Е : MOVE 11 and clock input 12.

The cell phasing receiver operates as follows.

The information binary sequence from the information input 11 of the device arrives at the first input of the decoder 1, which, upon receipt of a sync pattern type combination, generates at the output a response to the sync group in the form of a pulse. Clock pulses arrive at the clock, device input 12, gates the response pulses, and also arrive at the counting input of the counter 10 of the cycle and at the clock input of the first shift register 3.

In the initial state, the cycle counter 10 is in a random phase, its output pulses do not match the time with the responses to the sync group from the output of the decoder 1, therefore the first input of the second shift register 9 does not receive the output of the second element 7 and the clock input The second shift register 9 receives shifting pulses, as a result of which the second shift register 9 will be zeroed out, and the third element AND 8 is opened along the second group of inputs. In addition, the output ilt-pulses of the 10-cycle counter support the trigger b of the second input in such a state that its output signal allows the passage of units from the output of the first shift register 3 through the first AND 5 element and the OR 2 element to its first (information) input. The cyclic phasing receiver begins searching for cyclic synchronism. The first response to the sync group from the output of the decoder 1, through the first input of the element OR 2, goes to the first input of the first shift register 3, is written to its first bit, and the clock pulses from the clock input 12 begin to advance the recorded unit through the first shift register 3. Since the length of the phasing cycle is equal to p bits, and the length of the first register 3 shift is equal to (n-1) bits, then through the cycle the first unit is recorded in the register, passed from the output of the last {Bit of the first register 3 shift through the open trigger signal b first The 5 th element and the OR element 2 will be in the second bit of the first register 3 shift. If this first unit corresponded in time to the true sync group, then a second true response should occur at the same position of the cycle at the output of the decoder 1, and the corresponding unit will be written to the first bit of the first shift register 3 through the OR 2 element. Now, in the first 3 shift register, two units of a different order will be advanced. Thus, if the responses to the synchronic group from the output of the decoder 1 appear regularly after π clocks at the same cycle position, then in the first bits The first 3 shift register will be written with the corresponding units. ; False responses will correspond to a 3 unit shift randomly distributed over the first register. At the moment when the number of units in the first bits of the first register 3 shift is changed, the decoding rule for the synchronization is decisive, the decoder 4 / connected to the group of outputs of the first bits of the first shift register 3 generates a signal that passed through the third group of inputs 8 to the second group of inputs will set the cycle counter 10 into the state at the input of the initial state setup, as a result of which its output pulses will correspond to cycle phasing pulses. In addition, the signal from the output of the decoder 4 sets the trigger b on the first input to the state in which its output closes on the second input the first element And 5, which will be closed during the next cycle, since the trigger state b will be changed only cyclic pulses from the output of loop counter 10, which will come to the second input of Trigger b in n cycles. As a result, during the cycle, when the first AND 5 element is closed, the first shift register 3 will be cleared of the accumulated units in the search mode corresponding to both true and false responses to the sync group, since the ring between its last and first bits will be opened. With the arrival of the next cycle pulse from the output of the counter. 10 cycles to the second input of the trigger b of the first element I 5, the accumulation of units again begins again in the first shift register 3 to determine the Phasing time of the cycle counter 10. At the same time, the cyclic phasing pulse from the output of counter 10 of the cycle coincides on the second element I 7 with the next true response to the sync group from the output of the decoder 1, will be written into the first bit of the second shift register 9, as a result of which the third element I 8 closes along the second group of inputs and will be closed until at least one unit is in the second shift register 9. And the units in the second shift register 9 will be present until the pulses from the output of counter 10 of the cycle coincide in time with the true responses to the sync group from the output of the decoder 1. Thus, the cyclic phasing receiver has switched to the established mode. If now within the cycle the responses to false sync groups are even grouped and trigger the decoder 4, then its output will not cause a change in the phase of the counter 10 of the cycle, since it will not pass through the third element And 8 closed on the second inputs will change in that ray if, in the presence of false synogroups within a cycle, true synogroups will be distorted. Obviously, the allowable number of additional synchronized clock groups determines the length of the second shift register 9. From the established mode to the search mode, the receptacle cyclic phase-shifting device will switch only in that case.

$ 1085006

if in the second shift register 9, none of the technical and economic efficiencies will occur, and the proposed receiver’s ethnicity can occur only if cyclic phasing occurs if the number of subsets distorted with increased noise immunity at synchro groups will be greater than the number of the established mode due to the offset of the second shift register 9 shift .5 Lazy setting of the counter phase Cycler random distortion of the nelo 10 synchro groups with the help of the entered second will output the receiver of the cyclo register and 9 shift, trigger 6 and elephasing from steady state. And 5.7 and 8.

Claims (1)

A CYCLE PHASING RECEIVER containing a sequentially connected sync group decoder, an OR element, a first shift register and a predetermined state decoder, a cycle counter whose clock input is combined with the clock input of the first shift register and the clock input of the sync group decoder * and is a device clock signal by that. that, in order to increase the noise immunity in the steady state, a serially connected trigger and a first element And, a series-connected second element And, a second shift register and a third element And, the output of which is connected to the information input of the cycle counter, are introduced into the output, the output of the first shift register through the first element. And connected to the second input of the OR element, the output of the decoder of the given state is connected to the first input of the trigger and the additional input of the third element And, the output of the loop counter is connected to the second input of the second shift register, the second input® to the trigger and the first input of the second element And, the second input of which sub / keys to the output of the sync decoder. £