SU1341727A2 - Cycle synchronization device - Google Patents

Abstract

The invention relates to the transmission of data and reduces the time to establish 1: microchip phasing. The device contains a shift register 1, decoders 2 and 3, elements AND 4 ,, block 6 for checking alternation of codes, elements NO 7 and 15, drives 8 and 9, elements OR 10 and 14, distributor 11 pulses, block 12 for allocating the clock frequency, code Converter 13, single-tube 16. 1 Il. S (About to 14)

Description

The invention relates to prior data and can be used to provide cyclic phasing of synchronous communication systems.

The purpose of the invention is to reduce the time to establish cyclic phasing.

The drawing is structural

electrical circuit of the cyclo-10 device

howl sync.

The frame alignment device contains the shift register 1, the first and second decoders 2 and 3, the first and second elements AND 4 and 5, the block 6 for checking code alternation, the first element NO 7, the first drive 8, the second drive 9, the first element OR 10 , distributor 11 pulses, block 12 allocation of the clock frequency, code converter 13 ,. the second element OR 14, the second element NO 15, one-shot 16, the third element And 17.

The frame alignment device operates as follows.

A group digital signal (a continuous sequence of binary ones and zeros) is fed to the input of the shift register 1, the code converter 13 and the extraction unit 12 also enter the first input of the first frequency frequency, which extracts the clock frequency (frequency wiring), which is necessary for the operation of the distributor 11 pulses.

The incoming group signal is advanced along the shift register 1 rows. From the output of the shift register 1, the combination of received message elements (postal code) in the parallel code is fed to the inputs of the first and second decoders 2 and 3. Each combination of signals at the inputs of the first and second decoders 2 and 3 , similar to one of the phasing combinations, cause the formation of a signal at the output of the corresponding decoder 2 or 3

If the device is in a state of synchronization, the individual signals from the outputs of the first and second decoders 2 and 3 coincide in time with the clock signal of the pulse distributor 11, which arrives once per cycle from the loop output of the pulse distributor 11. pulses. In this case, the outputs of the corresponding elements AND 4 and 5 alternately (after one cycle, signals appear that correspond to the time of recognition of the phasing combinations. The code interleaver check unit checks the alternation of incoming signals to its inputs. Signal at the output of the interleaver check unit codes appear only when signals are interleaved at its outputs.

Since in the case of common mode operation

the alternation of codes is present in each cycle, and the signals at the output of the first element HE 7 are absent, the second drive 9 is charged, and at its output there is a signal of in-phase operation. This signal allows the decoding of information received at the first input of the code converter 13, and its output to the output device, enables the first drive 8 to work (puts it into readiness mode for maintaining in-phase operation, i.e., allows the charge of the first drive 8) and prohibits the passage of signals from the output of the second element OR 14 to the input of the one-oscillator 16.

In addition, the signals from the output of block 6 checks the alternation of the codes of the code OR 10. The output signals from the output of the first element. OR 10 triggers. An output of 11 pulses, which controls the recording and de-shaping of information in the code converter 13.

Thus, the start of the pulse distributor 11 is carried out once at the beginning of the cycle of the received

0 at the output of the group signal at the same points in time, i.e. the device is in the common-mode state.

False synchro groups similar to

5 phasing combinations and allocated to the first n second decoder 2 and 3 of the group signal, due to the random combination of zeros and units of information in the group signal do not coincide in time with the signal generated at the first output of the distributor 11 pulses one time per cycle, and therefore Do not pass through the first and second elements of AND 4 and 5 and do not participate Lot in the operation of block 6 of the code alternation checking.

With short-term distortions of phasing combinations (for example, due to interference or when

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synchronization in systems of higher order) the signal at the output of block 6 for checking the alternation of codes is temporarily absent. In this, the first element NO 7 is open and the signal from the first output of the distributor of II pulses, generated at the end of the cycle of operation of the distributor of I pulses (actually at its stop), flows through the first element of NET 7 to the second outputs of the first and second drives 8 and 9 This signal resets the counting circuit of the second accumulator 9 to the zero state. The level of the common-mode signal at its output remains, since it is reset only when a reset signal is received from the first output of the first drive 8,

Since at the output of the second accumulator 9 there is a signal permitting the operation of the first accumulator 8, the signal from the output of the first element NO 7 passes through the first accumulator B to autorun, while simultaneously charging the first accumulator 8 not one unit. This signal, passing through the first element OR 10, starts the distributor of 1 1 pulses for the next cycle of operation.

Thus, the start of the distributor 11 pulses occurs at the same point in time as in the presence of phasing combinations. Therefore, a synchronicity violation does not occur and the device continues to operate in the state of maintaining synchronism. In addition, the autorun signal from the second output of the first storage device arrives at the third input of the code converter 13.

Depending on the mode of operation of the code converter 13, the autostart signal either does not affect its operation or (higher reliability mode) prohibits detection and output of information at the output of the device.

If there are no phasing combinations in the following cycles, the operation continues in the same way until the first drive 8 is charged. The occurrence of a signal up to this point in time at the output of block 6 for checking alternation of codes (i.e., detection of phasing combinations at previous time positions) causes a reset earlier

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The damaged first drive 8 is in the zero state. The same signal through the first element OR 10 passes to the first input of the distributor 11 pulses, start it. Thus, the device re-enters the common-mode operation.

In the absence of signals at the output of block 6 for checking the alternation of codes in I, the next cycles (where I is the accumulation factor of the first accumulator 8), i.e. when the first accumulator 8 is charged, a reset pulse is formed at its first output, which transfers the second accumulator 9 to the zero state. As a result, a zero level appears at the output of the second accumulator 9, and therefore, the code converter 13 stops decoding the information and outputting it to the output of the device. In addition, the absence of a signal at the output of the second accumulator 9 removes the first accumulator 8 from the state of readiness to support in-phase operation and allows the signals to pass through the second element NO 15.

In the synchronism search mode, the device operates as follows.

Due to the stop of the distribution, the pulse bodies 11, there is a voltage level at its first output that permits the passage of signals through the first and second elements AND 4 and 5. Therefore, when the first or second decoder decodes 2 or 3 of the received message elements, one of the combinations similar to phase-. At the output of the second element OR 14, a signal is generated that arrives at the first input of the second element NO 15.

Due to the absence of an in-phase operation signal at the output of the second accumulator 9, the second element NO 15 is open and the signal from its output goes to the second input of the third element AND 17 and to the input of the single vibrator 16. Since the one-shot 16, which forms when it starts, logical zero, triggered with some delay, the signal from the output of the second element NO 13 passes through the third element And 17 at its output and enters the third input of the first element OR 10. As a result, a test

start of the distributor 11 pulses. At the same time, a signal about the detection of a combination, similar to a phasing one, from the output of one of the elements 4 or 5 is fed to the corresponding input of the block 6 for interleaved code checking. The probable launch of the distributor 1 i of pulses causes the signal at its first output to change to a zero level, which is stored until the moment of time corresponding to the stop of the distributor 11 pulses (i.e. during one cycle of operation). Therefore, elements 4 and 5 are closed. The allocation of the decoders 2 and 3 combinations, similar to the phasing and located in time within the cycle of operation of the code converter 13, does not affect the operation of the code sequencing checker.

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The operation proceeds in a similar way, until a signal appears at the output of the second accumulator,

, - indicating the occurrence of appa- 5

Ratura in synchronism and closing

the second element is NO 15.

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Let, for example, test start of the distributor 1 1 of pulses conducts, with a signal from the output of the second decoder 3 through the second element AND 5, the second element OR 14, the third element And 17, the first element OR 10. After a time equal to the duration of the cycle of received message elements , the pulse distributor 11 returns to the initial state and at its first output a voltage level appears allowing the signals to pass through the first and second elements 4 and 5.

If at this moment of time a combination similar to the phasing is allocated by the first decoder 2 (i.e., the phasing combination is changed), the block B of code interleave check is triggered, as a result of which a signal is generated at its output that triggers the pulse distributor 11 positions and the recording unit in the second accumulator 9. In the next cycle of operation, at the time of the formation of a destructive signal at the output of the pulse distributor 11, a 50 signal is formed at the output of the second decoder 3 (i.e. goes change phasing combination). Block 6 checks the rotation of the codes again, as a result of which the start of the distributor 11 pulses is carried out at the previous time positions, and in the second drive 9 it records from the second unit.

In case the test start of the pulse distributor 11 is made randomly by a combination similar to the phasing, in the next cycle of received message elements at the previous time positions, another friend is located 15 different from the phasing, as a result of which the second test run of the pulse distributor 11 through the second element OR 14, the second element is NO 15, the third element OR 10 does not occur at the previous time positions and the device continues to be in the off state. suit combination similar to phasing.

In the case of repeated cyclical repetition of the same information in several cycles and at the initial trial run of the distributor from a random combination similar to the phasing one, the same combination is again allocated by the same decoder (for example, the second) at previous time positions after a cycle of operation the distributor 11 impulses - 35 sov. However, the secondary problem. In this case, the distributor of 11 pulses does not occur at the previous time positions, since the signal from the output of one of the vibrator 16 prohibits the passage of test run signals through the third element And 17 through its first input (the duration of the inhibit signal at the output of the one-vibrator 16 messages and duration of one element of the message).

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Claims (1)

Invention Formula Frame alignment device for avT. St. No. 1259504, about tl and h and yuy; e with the fact that, in order to reduce the cycle phasing establishment time, the second element OR, the second element NO, the one-shot and the third AND element, whose output is connected to the third input of the first OR element, and the second input to the third input, are introduced in series Frame alignment device for avT. St. No. 1259504, about tl and h and yuy; This is due to the fact that, in order to reduce the cycle phasing establishment time, the second element OR, the second element NO, the one-shot and the third AND element, whose output is connected to the third input of the first OR element, and the second input to the third input 71341727 are introduced The second element is connected to the output of the second body, while the outputs of the first and second elements are NO, to the second input of which elements AND are connected to the inputs of the second output of the second accumulator of the second element OR.