SU1295507A1 - Digital stochastic filter - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in stochastic optimal automatic control systems and computer networks. The purpose of the invention is to increase the speed. This goal is achieved due to the fact that the optimal filter contains (N-1) block 1, -1, the smallest number, N permanent memory blocks, demultiplexer 3, element 6, counter 4, synchronizer 5 and corresponding connections between filter nodes, 2 nl.

Description

The invention relates to specialized computing and can be used in stochastic optimal systems of automatic control and computational permanent memory, where they occur.

set x.

The purpose of the invention is to increase speed,

Figure 1 shows the multiplication functional by the p-bit dny code of the corresponding weighting factor a. To synchronize input signals

20

blocks. c.,) at least the minimum on the filter circuit; figure 2 - syncro-fO number delay time in circuit 2 (M-OI nizator.delay selected equal to i (lbt-T),

The filter (Fig. 1) contains blocks i 1,2, ..., N-2, where t is the time in 1 d - 1 (j-- in the smallest number, holding the selection box of the smallest blocks 2.- 2 |, fixed memory, decad. As a serial co-multiplexer 3, counter 4, synchronization-15, block dinging ..IM implements mash 5, element 6, and informational procedure for selecting the smallest number of input 7.

The synchronizer 5 (FIG. 2) contains a clock generator 8, an AND 9 element, a T-bit shift register 10, an RS trigger 11, and a frequency divider 12.

The filter works in the following way.

A random sequence of N 1-bit numbers with a known probability distribution and the following frequency from input 7 of the device enters the input of element AND 6. At the other input of element And 6, clock pulses come from the third output 5 of synchronizer 5 (through element And 9 from the output of the clock generator 8), providing a timed arrival of the input sequence to the information input of the demultiplexer 3.

-At the same time, pulses from the output of the clock-35 .., °: oscillator 8 of the generator 8 through the element 9, to the second input of which a single signal comes from the zero output of the RS flip-flop 11 (in the initial state RS-trigger 11 is reset), go to 40 passing through the element 6 and the frequency divider 12 (the multiplexer factor 3 of any information ant is equal to 1/1). From the output of the split 12 D of the completion of the code formation to the 4acTofu (i.e., the first output 5 of the syn. Block 1,. At the end of the shape-chroniser 5), the pulses go to the number of the output of the device, the counting input of the counter 4. The code from the 45 output register 10,

from the output sample of a given volume N, then at the output (N-1) -ro of the allocation unit 1 of the smallest number a number is formed in the (1 + p-1) -discharge code with the required distribution law.

To increase the noise immunity of operation through the 1 at time from the 1st output of the shift register 10 (at the initial moment, 1 is written to the first bit of the shift register 10, and the rest is O),

T 1p + t rr

N1-1 where

one)

& t

, o “St

- sign of the target number;

-time delay blocks 10 and 11,

the signal is removed, the translator RS prohibits the passage of pulses from the code of the clock generator 8 through the AND 9 element.

This eliminates the possibility

The counter 4 is supplied to inputs 3 through 3 of the switching control of the demultiplexer 3 1 xN. To synchronize the control signals at the inputs 3, -3, t and information signals at the information input of the demultiplexer 3, the delay time tj, element 6 is set equal to t + ut, where tj is the delay time

, C.l- |.-IlP-tiJl |, N.l + p-1 +

JjjLb. ± bjlJjo -li, it

where C is any integer providing this inequality; the signal coming to the R input of the RS flip-flop 11 is removed - the RS flip-flop 11

i-ro block; & t - time interval 55 is transferred to the initial input (zero) pulse input pulse (this coherence signal, which is also equal to the interval through the second output 5, s.the synchronizer of the 1-bit input 5 itself, goes to the clock inputs of the code blocks). sequences (numbers) ... allocation of the smallest чисS outputs 1,2N demultiplexer 3 1-bit code sequences are fed to the inputs of the corresponding blocks 2, 22 ,,,., 2 "

multiplication by the p-bit dny code of the corresponding weight coefficient a. To synchronize input signals

i 1,2, ..., N-2, where t is the delay time of the smallest allocation unit. Since the sequential connection of the blocks ..IM implements the procedure for selecting the smallest number

from the output sample of a given volume N, then at the output (N-1) -ro of the allocation unit 1 of the smallest number a number is formed in the (1 + p-1) -discharge code with the required distribution law.

To increase the noise immunity of operation through the 1 at time from the 1st output of the shift register 10 (at the initial moment, 1 is written to the first bit of the shift register 10, and the rest is O),

T 1p + t rr

N1-1 where

one)

& t

, o “St

- sign of the target number;

-time delay blocks 10 and 11,

a signal is removed that translates .., °: ° passing through an AND 6 element and a multiplexer 3 of any information before terminating the generation of a code on the output unit 1,. Upon completion of the formation of the number at the output of the register output device 10,

the passage of pulses from the code of the clock generator 8 through the element 9 is prohibited.

This eliminates the possibility

, C.l- |.-IlP-tiJl |, N.l + p-1 +

JjjLb. ± bjlJjo -li, it

where C is any integer providing this inequality; the signal coming to the R input of the RS flip-flop 11 is removed - the RS flip-flop 11

la, drive them back to the initial state), the operation of the device is repeated.

Claims (1)

Invention Formula A digital probabilistic filter containing the AND element whose output is connected to the information input of the demultiplexer, the i-th (, N, N is the filter order) whose output is connected to the address input of the i-ro block of the permanent memory, synchronizer, first the output of which is connected to the counter input of the counter, the information output of which is connected to the control input of the demultiplexer, the outputs of the first and second blocks of the fixed memory are connected respectively to the first and second information inputs of the first allocation block of the smallest number, t the entrance to which five J3 l 7G Editor O. Yurkovetska Compiled by A. Baranov Tehred V. Kadar Proofreader I. Muska 627/61 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 connected to the second output of the synchronizer, and the first input of the AND element is an information input of the filter, characterized in that, in order to improve speed, (N-2) allocation units of the smallest number are entered into it, and the output j-ro (, .N -2) the smallest allocation block is connected to the first information input (j + 1) of the smallest block, the second information and clock inputs of which are connected to the fixed memory (j + 2) -ro output and the second synchronizer output whose third output is connected n. to the second input of the AND element, and the output of the (N-l) -ro block of the selection of the lowest & lowest number is the information output of the filter. eleven o "52 rm (Rig2