SU1304079A1 - Buffer storage - Google Patents

Abstract

The invention relates to means of storing and storing information and can be used in control and data processing systems. The purpose of the invention is to expand the field of application of the device by sequentially recording information from arrays of arbitrary size. The cell address of any array is formed by adding on the second adder the contents of the lower bits of the counter and the result of producing two numbers: a conversion factor and a partial sum from the first adder. 2 Il. S (L with about N About; about

Description

The invention relates to computing and can be used in the buffer memory devices for input and processing of information of multi-channel measuring systems.

The purpose of the invention is to expand the field of application of the device due to sequential-circular recording of information from arrays of arbitrary volume.

The drawing shows a block diagram

a pulse appears at the output of the delay element 7, as a result of which, firstly, a group shift is made in the shift register 4 and in the part that is connected to the memory 11, the second message measurement is recorded, secondly, one bit to the left of the contents of the register 5 shift. However, since this register was in the 0 ... 0 state, then after the impact of a pulse, the proposed device (the mechanism doesn’t change its state.

clearing information from the buffer arraysLet time ft from the beginning of the cycle (tj, t,)

a clock pulse appears at the output of delay element 8, resulting in

to the right (youngest) bit of the register 5

not shown).

The device contains counter 1, trigger 2 element 3, the first shift register 4, the second shift register 5, the group of elements 6 and 6, the shift is entered 1 and the register receives the first delay element 7, the second element 0 ... 01. In accordance with its state, the state of the right (least significant) of the high bits of counter 1 is transmitted to the corresponding input of the first sum of 20 torus 10 through the corresponding element 6. Since the first term for the adder 10 is the number O ... 0bt and wto8 delay, the third element 9 delay, the first adder 10, the drive 11, the register 12, the multiplier 13, the second adder 14, the first 15, the second 16, the third 17 inputs of the device.

The device works as follows.

Before the beginning of the next cycle of operation of the device, the shift register 5 is

eye - the number 0 .... 01, then at the output of the adder 10 a result is formed that is different from zero. This result is multiplied by

in the state 0 .... 0. At the output of the trigger 2 25 conversion factor multiplier 13.

The product from the output of the latter, which is added to the state of the lower bits of the counter 1 - by the number am --- ai, forms the address from the second memory array, which should be used to record the second dimension with

there is a inhibitory potential that prevents the passage through the element And 3 clocks from the third input 17 of the device.

The next cycle begins with the arrival of the next clock pulse along the first 30 shift register 4. At this, the first clock in the device input 15 and the corresponding operation of the device ends with the next message to it by the second. Denoted by the symbols A - the state of the youngest input 16 devices of the bits, B - the higher bits

The sync pulse is counted by counter 1 of counter 1, C is the contents of register 12, and triggers trigger 2, as a result of which D - the state of shift register 5, after the output of the latter, the resolving potential of the second potential is generated. as (B + D) xC + A.

The clock 2 starts from the moment when the second clock pulse appears at the output of the And 3 element, as a result of which in Tact 1 it starts from the moment left to the collector 11 at the address CB .... 01) + (O .... OH,) x neither at the output of the element And 3 of the first so-xC + (apt ... a1) the second dimension is recorded from the shift register 4. A signal from the output of the delay element 7 produces a group shift in the shift register 4 (and on the part that matches the storage record. Since the shift register is 5 by level 11, the third dimension is fixed) and goes to the state 0 ... .0 and at the outputs a shift in shift register 5, which assumes a state of D 0 .... 010. However, after the time Tj -CG, a signal appears at the output of delay element 8 and the status of the resistor is O. Therefore, the result of the summation of the 5th shift is D 0 ... 011. Vani on the second adder 14, and the next - In accordance with its state through

the corresponding elements of And 6 translate the values of the first and second right of the higher bits of counter 1 to the corresponding inputs of the first adder

the shift, which is connected to the informational 55 O, forming B O .... OP, the input of the accumulator 11. As a result of performing L (0 .... 0bibi) +

After the time f, (longer than the time + (O .... 011) x C + (am ... a,), the measurement record is written to the memory), the clock time of the cell of the third array, in which

input element and 3.

In the future, the device operation takes place in several cycles.

total pulse in the cycle. A pulse pulse acts on the control input of accumulator 11, as a result of which the latter runs the mode cyclogram

of all elements AND 6- "O, then the result of the summation on the first adder 10 and multiplication on the multiplier 13 is terminal, and the memory address is the state of the lower bits of the counter 1. At this address, the measurement contained in that part register 4

a pulse appears at the output of the delay element 7, as a result of which, firstly, a group shift is made in the shift register 4 and in the part that is connected to the memory 11, the second message measurement is recorded, secondly, one bit to the left of the contents of the register 5 shift. However, since this register was in the 0 ... 0 state, then after the impact of the shear pulse, its state does not change.

to the right (youngest) bit of the register 5

the shift is entered as "1" and the register assumes the state 0 ... 01. In accordance with its state, the state of the right (least significant) major bits of counter 1 is transmitted through the corresponding element 6 to the corresponding input of the first totalizer 10. Since the first term for the adder 10 was the number O ... 0bt and the second is the number 0 .... 01, then a result other than zero is formed at the output of the adder 10. This result is multiplied by

conversion factor multiplier 13.

The product from the output of the latter, which is added to the state of the lower bits of the counter 1 - by the number am --- ai, forms the address from the second memory array, which should be used to record the second dimension with

register 4 shift. At this point, the first cycle of operation of the device ends, Denoting by the symbols A - the state of the lower order bits, B - the older digit

The third measurement should be recorded from the shift register 4.

At this point, the second cycle of the operation of the device ends. Subsequent cycles of operation of the device are similar.

Before the start of the last clock cycle, the last measurement register 4 contains the last measurement, and the output of the second array is formed at the output of the second adder 14

L (6n ... bO + (1 ... l) Jx C-H (dm ... tti).

The last clock cycle starts from the moment when the last clock pulse in the cycle appears at the output of the And 3 element. As a result of the impact of this pulse, the last measurement from the shift register 4 is recorded in the drive 11.

The occurrence of a signal at the output of delay element 7 leads to a group shift of information in register 4 (after which the register is completely cleared and takes state 0 ... 0) and shift in register 5, which takes state 1 ... 10. After the time r -TI, as a result of the signal from the output of the delay element 8, the register state is restored - 1 ... 1. However, after time - (ty + + Tg -T,), where t,. Is the period of arrival of clock pulses from the output of element 3, a signal appears at the output of delay element 9, as a result of which the shift register 5 takes the initial state 0 ... 0, and the trigger 2 is transferred to the state with the inhibiting potential at the output.

This is the end of the last clock cycle and, accordingly, the cycle of operation of the device for servicing the incoming message.

The delay time fj is chosen to be longer than tr-f (Cr - T |), since the potential "1 at the output of the left (senior) bit of the shift register 5 appears in the penultimate cycle.

The proposed device allows sequential-ring recording of information into memory arrays, the youngest of which can have an arbitrary volume. The implementation of the device is simple and can be performed by a minor amount. Edited by I. Casard Order 1316/52

VNIIPI USSR State Committee for Inventions and Discoveries

P3035, Moscow, Zh-35, Raui1ska nab. 4/5 Production and Printing Enterprise, Uzhgorod, ul. Design, -1

with integrated circuits of medium integration.

Claims (1)

Invention Formula A buffer memory containing a counter, a drive, a trigger, an And element, a group of And elements, a first adder, first and second shift registers, the first, second and third delay elements, the first trigger input connected to the counter input and the first input of the device The first input of the first shift register is the second input of the device, and the first input of the AND element is the third input of the device, the second input of the AND element is connected to the trigger output, and the output is connected to the inputs of the first and second delay elements A storage input, the information input of which is connected to the output of the first shift register, the second input of which is connected to the output of the first delay element, and the first input of the second shift register, the second input of which is connected to the output of the second delay element, and the third input is connected to the second input trigger and with the output of the third delay element, the input of which is connected to the output of the high bit of the second shift register, one output of which is connected to the corresponding inputs of the first adder and with the first inputs of the corresponding elements AND groups, the second inputs of which are connected to the corresponding outputs of the counter, and the outputs are connected to the corresponding inputs of the first adder, characterized in that, in order to expand the device uses a series-ring recording of information from arrays of arbitrary volume; a second adder, a multiplier and a register are entered into the device; its output is connected to the first input of the multiplier, the second input of which is connected to the output of the first adder, and the output is connected to the first input. m of the second adder, the second input of which is connected to the output of the counter, and the output is connected to the address input of the accumulator. Compiled by V. Gordonov Tehred I. VeresKorrektor M. Pojo Circulation 590 Subscription