SU1363214A1 - Device for forming remainder by random modulus from number - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to build various devices for the transmission and processing of discrete information. The purpose of the invention is to increase the speed of the device. The information inputs of the device group 8 are connected to the information inputs of the counters of group 2 in such a way that the j-th information input of any counter of group 2 is connected to the 1st bit of the monitored code that satisfies the condition (oe) niod to ((O;) mod K where Wfr and (Oj is the mass of the 1st bit of the controlled code and the j-ro bit of the counter of group 2, respectively. Before starting, they are set to the zero state. At p - (- 1st output of the switching unit 4, zero signal, prohibiting the passage of signals from the output of the generator 1 clock pulses through the e And 6 on the counting input of the counter 7 modulo K. When writing a non-zero code to the registers of group 2, single signals are formed at the outputs of the corresponding elements of group 3. The outputs of all the elements of OR group are connected to the corresponding control inputs of the group of switching unit 4. Signals from the output a clock pulse generator 1 arrives at the information input of the switching node 4 and appears at the information output of the switching node 4. The signal at the (p + 1) -th output of the switching node 4 becomes equal to one. Shaper 5 pulses sets to zero state i (L 1l- (f-2} with O5 CO ND

Description

counter 7 modulo K, and element 6 begins to pass clock pulses to the counting input of counter 7. The signal from the information output of switching node 4 goes to the subtracting input of the corresponding counter of group 2, reducing its content. When a zero code is set on the counter of group 2, the signal at the output of the corresponding AND element of group 3 becomes equal to zero.

The invention relates to automation and computing and can be used to build various devices for the transmission and processing of discrete information.

The purpose of the invention is to increase the speed of the device.

FIG. 1 is a functional diagram of the device where the circuit implementation of the switching node is disclosed; in fig. 2 - a functional diagram of one of the variants of the switching node; in fig. 3 - functional scheme of one of the variants of the adder modulo K.

The device for forming the remainder of an arbitrary module of the number (Fig. 1) contains a clock pulse generator 1, a group of 2 counters, a group of 3 OR elements, a switching node 4, a pulse shaper 5, an Andb element, a counter 7 modulo K, a group of 8 information device inputs, device output 9. Node 4 switching contains a group of elements And 10, 11.

Node 4 switching contains (Fig. 2) a group of elements 12 And the element OR 13.

The counter 7 modulo K- (Fig. 3) contains the counter 14, the comparison node 15, the pulse shaper 16, the group 17 of the inputs for setting the code of the counter module.

The device works as follows.

Counters 2 of the i-th group are subtractive. In the initial state, they recorded a zero code. At the same time, there is a zero logic signal at the (P- | --1) -m information output of the switching node 4, which prohibits the passage of clock pulses from the output of generator 1 through element 6. When counter 7 is modulo K with a variable value of module K on its the inputs of the module code setting for group 17; the code of the number K is given.

The binary code of the number A is recorded in the 2 group counters. And in the j-th bit of the counter 2 of the group is recorded the 1st bit of the input code A, having a weight She, the remainder

The control code and the clock pulse generator 1 signals appear at the next information output of the switching node 4. When all the counters of group 2 are zeroed, a zero signal is generated at the (p -) - 1) -th information output of the switching node 4. It prohibits the passage of signals to the counting input of counter 7 modulo K, where the remainder modulo remains. 3 il.

modulo K which has the same meaning as the remainder modulo K j-ro bit of the translated code. For example, with n 30 (the number of bits of code A), K 3,

P 10 and the binary natural code A, the first and second bits of the input code are recorded in counter 2-1, the (2i-1) -th and (2) -th bits of the input code are recorded in counter 2-i. When counter 2-i, the input code bits from (61-5) .go to (6i) -ro are recorded. In the case and in the counter 2-i, the input code bits from (3i-2) -th to (3i) -ro are recorded. The code is written to the 2 group counters by feeding it to the information inputs 8 in

a pause between clock pulses at the output of the generator 1. At the (P + 1) -th information output of the switching node 4 with a non-zero code recorded in the counters of group 2, there appears a single logical signal allowing the passage of clock pulses to the output of the And 6 element. the presence of 5 pulses in the device of the driver at the appearance of a single logical signal at (Pfl) -M information output of the switching node 4

it generates a reset signal modulo K, set it to its original state (counter 7 modulo K can be set to its original state and by sending a signal to its setup input simultaneously with writing the code to meters 2

groups).

Next, the clock pulses, arriving at the input of the element 6, pass to the counting input of counter 7 modulo K, which calculates them modulo K. At the same time they pass to the information input of the switching node 4. Let the 2-i number be the smallest group 2 counter in which a non-zero code is written, and at the output of the group element OR 3-1 there is a single logical signal arriving at the i-th control input of switching unit 4, whose control inputs 1 - - (i-1) receives a zero logical signal from the outputs of the elements OR (3-1) 3- (i-1). At the same time, the clock pulses pass from information node 4 to its i-th information output and arrive at the subtracting input of counter 2-i of the group, from whose content a unit is subtracted each time. Work continues in this manner until the counter of group 2-i is zeroed. When it is zeroed, a zero logic signal appears at the output of the OR element 3-i of the group, prohibiting the passage of clock pulses to the i-th information output of the switching unit 4. Further, the remaining counters of group 2 are similarly circled. When the last counter is reset, the (Pf 1) information output of the switching node 4 results in a zero logic signal prohibiting the passage of clock pulses through the And 6 element to the count input of the counter 7 modulo K. The result of the work is removed from. outputs of counter 7 modulo KFORMULA of the invention

A device for generating a residual modulus of an arbitrary modulus of a number, comprising a clock pulse generator, an AND element, a pulse shaper, a modulo-K counter, a first group counter and a first OR element of the group, the output of the clock generator connected to the first input of the And element whose output is connected with the counting input of the modulo K counter, whose information output is the output of the device, the input of the pulse former is combined with the second input of the AND element, the output of the former

the pulses are connected to the installation input of the counter modulo K, the bit outputs of the first counter of the group are connected to the corresponding inputs of the first OR element of the group, characterized in that, to increase the speed of the device, (P 2) counters are introduced into it , (P-1) of the elements of the OR group and the switching node, the bit outputs of each i-ro meter of the group (2 i P) are connected to the corresponding inputs

The i-ro element of the OR group, the j-th information input of each counter of the group is connected to the corresponding information input of the device group connected to the 1st bit of the monitored code, having

weight We, and (She) (w /) mod

(1 j -, 1 I p, where p is the controlled code width, w / - weight of the j-ro discharge of the group counter), the output of the clock generator is connected to the information input of the switching node, each

the m-th information output of which is connected to the subtractive input of the m-th group counter (1 m P), the outputs of the elements of the OR group are connected to the corresponding control inputs of the switching node group, (P + 1) -th information output of the node

switching is connected to the second input element I.

 To node 6 13

From g / evil 1

15

17

g 5

G 1

From bonds / ia From node 6

ig.Z

Claims (1)

Claim A device for generating a remainder modulo an arbitrary number, containing an clock pulse generator, an And element, a pulse former, a modulo counter K, a first group counter and a first OR group element, the output of the clock generator being connected to the first input of the And element, the output of which is connected with a counter counter input modulo K, the information output of which is the output of the device, the input of the pulse shaper is combined with the second input of the element And, the output of the pulse shaper 5 is connected to the installation by the input of the counter modulo K, the bit outputs of the first counter of the group are connected to the corresponding inputs of the first element of the OR group, characterized in that, in order to improve the performance of the device, (P – 1) counters of the group (P 2), (P— 1) elements of the OR group and the switching node, and the bit outputs of each i-ro counter of the group (2 i P) are connected to the corresponding inputs 15 of the i-ro element of the OR group, the j-th information input of each group counter is connected to the corresponding information input of the device group connected m to the 1st category of the controlled code having BeС Cl) ?, Moreover, (iOe) modfe - (h) |) mod (1 Ci j -ρ-, 1 ¢ 4 I С n, where η is the bit depth of the controlled code, ω / Is the weight of the j-th discharge of the group counter), the output of the clock pulse generator is connected to the information input of the switching node, each 25th information output of which is connected to the subtracting input of the mth group counter (I m P), the outputs of the elements OR of the group are connected with the corresponding control inputs of the switching node group, the (P + 1) -th information output of the switching node 30 is connected to the second input of the element I. To node 6 .· 1 12-P 1 - 12-3 - 12-2 Riga 2 From node 1 FIG. 3