SU1415467A1 - Television standard converter - Google Patents

Abstract

The invention relates to a television technique. The purpose of the invention is to increase the number of convertible television standards. The device contains counters I, 2, 3, 4, switch 6, register 7, shift register 9, memory block 10, triggers 11, 12, And 15 element, output block 17, control block 18. In the device entered the counter 5, the second register 8, triggers 13, 14, element I 16, r-19 pulses. The pulses of elements are characterized by the fact that they occur only in the active part of the active lines. If the image format is 512x512, then in each of the 512 lines there must be exactly 512 pulses of decomposition elements. The output of counter 5 generates two sequences of pulses that are out of phase relative to each other by 180 and with a frequency 2 times lower than the frequency of the pulses coming from r-19. Each first pulse of r-19 polls the write request signal, and the second is a read request. As long as the pet signals for the write request and read the signals, neither a write cycle nor a read cycle are formed. The read and write processes are repeated periodically. 1 il. (L

Description

itd

vshov

NnLULO

3Aeneff- / chuo

ate

D: Oi

The invention relates to the technique of visual sight and can be used in constructing interface devices for television systems with independent scoops at different speeds, to obtain on the screen a broadcast video camera monitor device modulated by a computer or examined by a computer. slow scanning devices as well as to increase stability and synchronization of the scanning frequency when building image combining systems from several independent asynchronous video signal sources.

The purpose of the invention is to increase the number of convertible television standards.

The drawing shows a structural electrical diagram of the converter of the thermofix standard.

The television standard converter contains five counters 1-5, switch 6, d first 7 and second 8 registers, shift register 9, memory block 10, four flip-flops 11-14, first 15 and 16 elements And, output block 17, control unit 18 and generator 19 HNtnynbcoB.

The converter works as follows.

The clock input of the first counter I and the clock input of the shift register 9 receive pulses of elements from the sync rotor of the input sweep. The pulses of elements are characterized by the fact that they occur only in the active part of the active lines. If the image format is 512x512, then in each of the 512 lines there must be exactly 512 element pulses decomposed 1; . Non-synchronous inputs of the first 1 and second 2 counters receive synchronizing pulses. Here, sync pulses may arrive once per frame during a damping pulse, before the beginning of the next frame information. At the same time, counters I and 2 are set to O. The clock inputs of the third counter 3 are supplied with the pulses of elements from the output sweep clock, and the synchronous inputs of counters 4 and 3 are fed with clock pulses from the same synchronizer. It can also receive a snapshot once per frame up to H, j4a.-ia to read the information of the current frame. But with this counter

ten

 jo

20

25 jq

35

40

45

0

five

3 is set to O and the counter

4-state O-t-1.

The oscillator 19 pulses continuously generates a pulse train with a frequency P1, in the range of 14–15 MHz. These pulses arrive at the counting input of the fifth counter 5. At the output of the latter, the bottom of the sequence of pulses is shifted in phase relative to each other by 180 ° and with a frequency 2 times lower than the frequency of the pulses entering the input. One of these sequences goes to the second input of the first element 15 and the second to the second input of the second element 16. Thus, every first pulse of the pulse generator 19 polls the write request signal, and every second pulse reads the request. As long as there are no write and read request signals, neither a write cycle nor a read cycle is formed.

The input of the shift register 9 receives a video signal in digital form, expressed by a parallel code. Each code combination of the input digital video signal varies synchronously with the pulses of the elements of the input sweep. Therefore, each pulse of the element is provided to record each code sequence of the video signal in the shift register 9 and the first counter I to count the number of decomposition elements accumulated in the shift register 9 by the first counter I. The output signal of counter 1 is fed to the synchronization input of the first register 7 and to the second input of the first trigger 11. As a result, at the moment the first counter 1 transitions from full to zero, all information accumulated in shift register 9 is written to the first register 7, and at the output of the first trigger II a logical 1 is set. Thus, information for the recording is prepared and a write recording signal is generated.

The request signal for the list is sent to the first input of the first element I 15, and to its second input from the output of counter 5, a demand pulse. At the same time, at the output of the first 3ji (treHTa And 15, a signal is formed, it switches the second trigger of the 12 n state to the logical 1. BhlXo; iHI M SIG ELL THE FIRST

trigger 1 I set, Rlinlrts in the initial state, s, ksmm. t g; pr 6 connect20

the outputs of the second counter 2 to the address input of the block 10, the control block 1B switches to the recording mode and blocks the generation of the pulse generator 19. As a result, the fifth counter 5 switches and remains in this state until the end of the write cycle.

The leading edge of the output signal of the second trigger 12 triggers the IQ control block 18 and generates a write cycle. At the end of the recording cycle, the output from the control unit 18 receives a pulse at the input of the second trigger 12 and sets it to the initial state. At the moment of setting the second trigger 12 to its initial state, its output signal switches its second counter 2 with its back edge and as a result, the write address is increased by 1. In addition, the lock is removed from the pulse generator 19 and, if the read-ready signal is missing, the polling sequence repeats cyclically.

The pulses of the elements coming from the sync generator of the output sweep to the clock input of the third counter 3, switch it. The output of the third counter 3 is controlled by the output unit 17. As a result, the output successively displays information read out during the previous scoring cycle from memory unit 10 and rewritten into output unit 17.

When the third counter 3 transitions from full to zero, all information will be output from output block 17. Output sig25

35

0

Q 15 o

25

35

control block 18 is started and a read cycle is formed. During the counting cycle, the memory 10 of the adjacent elements is read out at the address determined by the fourth counter D. This information is written into the second register 8. At the end of the read cycle, the signal from the output of the control unit 18 to the input of the fourth trigger 14, setting the fourth trigger 14 to its original state. At this time, the fourth counter 4 is switched by the falling edge of the output signal of the fourth trigger 14. As a result, the address is increased by 1.

Thus, the write and read processes are repeated periodically. While the first register 7 transfers information to memory block 10, new information is accumulated in shift register 9, and while readout information is output from output block 17, information from the next 16 decomposition elements is read from memory block 10.

Claims (1)

Formula invented and A television standard converter containing serially connected shift register, first register and memory block, serially connected first counter, first trigger, first AND element, second trigger and control unit, first you cash counter 3, the input to the input to ° D which is connected to the manager output block 17, the start of overwriting information from the second register 8 is determined. The same output signal switches the third trigger 13. At the output of the third trigger 13, the logic level 1 is present until the output of the fifth counter 5 to the input of the second element 16 the survey impulse will come. When the signals of interrogation and interrogation of the output of the second element I 16 coincide in time, a signal is generated that switches the fourth trigger 14. The output signal of the trigger 14 of the control unit 18 switches to the contact mode and is blocked by the generation of pulses by the pulse generator 19. The leading edge of the output signal of the fourth trigger 14 the second block, the third counter and the output block connected in series, the clock inputs of the first counter and the shift register are combined and are the clock signal input; the sync inputs of the first and second counters are combined and are the input of the synchronization signal of the input standard, the synchronous inputs of the third and fourth counters are combined and are the synchronization input of the output standard, the clock input of the third counter is the input of the clock signal of the input standard, the address input of the memory unit is connected to the output of the switch, nepBbtfi and the second inputs of which are connected to the outputs of: the second and fourth counters, the control input of the switch and the clock of the second counter, and the output of the first counter, To the synchronization input of the first register, different in that, in order to increase the number of convertible television standards, the second register, the third and fourth triggers, the second element AND, the fifth counter and the generator are introduced pulse pulse, while the information input of the second register is connected to the output of the memory unit, the clock input of the second register is connected to the third output of the control unit, and the output of the second re the hystera is connected to the second input of the output unit, the third trigger, the second element And, the fourth trigger, the pulse generator and the fifth counter are connected in series between the output of the third counter and the second input of the first element And, the second output of the control unit is connected to the second input the fourth trigger, the output of which is connected to the clock inputs of the fourth counter and control unit and the second input of the third trigger, the output of the second trigger is connected to the second inputs of the first trigger and pulse generator, and the output a counter connected to the second input of the second member I.