SU1702358A1 - Dynamic process recorder - Google Patents

Abstract

The invention relates to automation and computing, in particular to specialized means for recording dynamic processes. The purpose of the invention is to simplify the device. This is achieved with the introduction of a delay block 8 and the corresponding functional links. When the power is turned on, the device is reset by the pulse generated by the shaper 1 of the initial setup signal. This clears the information in the memory block 9 by forming 0 at the output of the switch 5. After that, the output input of the block 9 is connected to the address input of the block 9 via the multiplexer 13 via the outputs of the counter 12. Block 9 has two fields, operation devices with which it is carried out alternately. By feeding information codes to inputs 18 and 19 of the device to block 9, the counts of the recorded process are digitized into the ADC 4. When reading information from block 9, the passage through counter 10 is converted into a video signal to which the video signal of the grid and the synchronization signals generated by the mixer 7 and the horizontal and frame scan 17 generators are mixed in the mixer 6. The total signal arrives at the output 22 of the device. 7 il. (L with

Description

VI

ABOUT

Yu

SA) SJ 00

The invention relates to automation and computing, in particular to specialized means for recording dynamic processes.

The purpose of the invention is to simplify the device.

Figure 1 shows the structural diagram of the device; 2 shows the same driver control signal; in FIG. 3 - the same as the horizontal scanning generator; figure 4 - the same, the generator frame scan; figure 5 is the same, the former of the coordinate grid; Figures 6 and 7 are timing charts of operation of the driver and the horizontal sweep generator.

The device contains a shaper 1 of the initial setup signal, a shaper 2 control signals, a shaper 3 of the recording signal, an analog-to-digital converter (ADC) 4, a switch 5, the first b and second 7 mixers, a delay block 8, a memory block 9, a second counter 10, a selector 11, a first counter 12, a multiplexer 13, a horizontal scanning generator 14, a clock pulse generator 15, a grid generator 16, a frame scan generator 17.

Positions 18 and 19 designate the information inputs of the device, 20 the input of the reset signal, 21 the trigger input, and the 22 the output of the device.

Shaper 2 control signals contains a differentiating chain 23, triggers 24 and 25, elements AND 26 and 27, element OR 28, and counter 29.

The horizontal scan generator 14 contains a frequency divider 30, a reversible counter 31, a delay element 32, an AND element, and OR 34 and 35 elements, a trigger 36.

The frame scan generator 17 contains counters 37.38 and 39, a differentiating chain 40, a decoder 41, and a trigger 42.

The imaging unit 16 of the grid contains one-shot 43 and 44, the elements And 45 and 46, the element OR 47.

The device works as follows.

At the moment the device power is turned on, driver 1 generates a pulse of positive polarity, which is fed to the reset (zeroing) input of counter 12, which is set to the zero state, and to the reset input of driver 2. In this case, the device enters the mode of erasing information in block 9 When the start-up pulse arrives from the input 21, the output of the driver 2 sets the voltage O, which comes from the control input of the switch 5. At the same time, the switch 5 disconnects the information inputs from its output. At the output of the switch 5, the voltage level is zero, which is fed to the information input of the ADC 4. In addition, when the trigger signal arrives, the driver 2 switches to the accelerated generation mode of the ADC signals 4 and the switching voltage, respectively, which arrive at the output of the driver 2, so as in this mode, these signals are formed from pulses arriving at the synchronization input with the horizontal frequency. The third output of the driver 2 triggers to the control input of the AHG 4. As a result, a digital code is generated at its output, corresponding to a zero level voltage supplied to the information input of the memory block 9. At the end of the conversion, the output of A / D converter 4 causes an impulse that triggers shaper 3, from which the write pulse of the negative field p5 nostm goes to the control input of the multiplexer 13, which provides a connection to the address input unit 9 of the information output of the counter 12 and switching voltage coming in from

0 of the first output of the driver 2, If the voltage 5 of the switching voltage corresponds to the level O, then the first memory region is selected, if 1 then the second memory region. In addition, the write pulse from the output of the forwarder 3 through the delay block 8 is fed to the control input of block 9. As a result, a digital code arriving at the information input of block 9 is written into the corresponding memory cells, the address

0 which is determined by the digital code at the output of the counter 12 and the switching voltage level at the output of the imaging device 2. The digital code at the output of the counter 12 changes when the switching voltage goes to 5 level and 1 level 0. At the end of the write pulse, the multiplexer 13 is connected to the address inputs of block 9 the output of the generator 17 and the switching voltage from the output of the selection of the memory region from

0 of the generator 14, which is low during the first half of the line, and high during the second half, which allows the separation of memory areas when reading information from block 9. Ad5 memory cell slots, from which information is read, are determined by binary the code generated by the information output of the generator 17. From the output of block 9, the digital code enters the information input of the counter 10 (reversible counter

pre-installed). When a recording pulse arrives from the generator 14 to the control input of the counter 10, the information from the output of block 9 is recorded into it, to the counting input of which, through the selector 11, pulses of the clock generator 15 begin to flow when there are simultaneously two enabling signals that are generated at the outputs of the generators 14 and 17. The task of selecting pulses sent to the synchronization input of counter 10 is solved by the selector 11. As the pulses enter the synchronization input of counter 10, the value of the previously written digital code in it when the zero code reaches the output of the counter 10, a raster illumination pulse is generated, which is fed to the mixer 6, which receives a mixture of frame and line sync pulses from the mixer 7 output. The mixer 6 receives the pulses from the generator 16 output, which generates the illumination pulses a raster for displaying two coordinate grids on the screen. From the output of mixer 6, a mixture of synchronizing pulses and illumination pulses is fed to the video input of the TV.

As the synchronization voltage pulse input from the synchronization input 12 of the switching voltage generates a binary code at its information output that determines the sequence number of the memory cells where information from the output of the A / D converter 4 will be recorded, which in this mode of operation of the device corresponds to a zero output signal. When counter 12 overflows, an overvoltage voltage is generated at its overflow output, which enters the shutdown input of the driver 2, which then stops generating the trigger signals of the A / D converter 4, the switching voltage, and at its output level 1, which permits Switching the information inputs of the device through the switch 5 to the information input of the ADC 4. This completes the mode of erasing the information in memory block 9, which passes through two frames of television scan. At the same time, the digital code corresponding to the zero level of the input signals is recorded in all the memory stack.

At the end of the erase mode, the device enters the standby mode for entering information.

In order to register the studied dynamic processes represented as DC voltages, they must be fed to the information inputs 18 and 19 of the device, and the input 21 of the device start signal is a positive polarity pulse at the moment of the start of registration. In this case, the device enters the recording mode.

The device allows you to simultaneously register two processes.

When the trigger signal arrives at the input of the imaging unit 2, voltage 1 is saved at its output, which allows the information inputs of the device to be connected through the switch 5 to the information input of the ADC 4. At the first output of unit 2, a switching voltage is formed, which provides alternate connection of the information inputs of the device switch 5 to the information input of the ADC 4, the control input of which receives start-up pulses from the output of the driver 2. Period of repetition of the start-up pulses of the ADC and switch voltage In this mode of operation, the period of repetition of pulses arriving at the synchronous input of driver 2 from oscillator 14 is determined. Otherwise, the operation of the device in the recording mode is similar to that in erasing information.

To stop recording, a positive impulse is required at input 21 of the device start signal, and another positive impulse to resume recording. When counter 12 overflows, the device automatically switches from recording mode to standby mode.

To erase the information stored in memory block 9, it is necessary to apply a negative polarity pulse to the memory zeroing input. In this case, the shaper 1 generates a positive impulse, which puts the device in the mode of erasing information.

Timing diagrams explaining the principle of operation of the imager are shown in Fig.6, where: 1 - a pulse coming from the output of the imager 1 to the input of the trigger signal of the imager 2; 2 - the pulse at the output of the trigger 24; 3 - the pulse at the output of the trigger 25; 4 - pulses at the input of the counter 29; 5 - start pulses from the output of the counter 29; 6 - switching voltage pulses from the output of counter 29; 7 - overflow signal, incoming PA stop input; 8 - the pulse at the output of the differentiating circuit 23.

The control pulse shaper operates as follows.

When a pulse arrives at the start signal input, counter 29 is set to

the zero state, and the first outputs of the griggers 24 and 25 are set to level 1. The second output of the trigger 24 sets the level O, which is fed to the output of the driver 2. As a result, the input of the counter 29 begins to receive pulses from the synchronization input through element 21 and element OR 28, When the overflow signal arrives at the Stop input of the driver 2, a pulse is generated at the output of the differentiating chain 23, which switches the triggers 24 and 25 to the reverse state. At that, the supply of pulses to the counter input is prohibited and, consequently, the formation of the start-up pulse signals of the 4–4 switching unit switching signal is stopped, and the level of H is set to 2 at the output of the generator. When the start pulse arrives, the level 1 is set to the counting input of the trigger 25 and the input of the counter ka 29 begins to receive synchronization pulses through the element 1/1 27 and the element OR 28. When the second pulse arrives, a level O is set at the counting input of the trigger 25, which prevents the arrival of a pulse Sync on the first input of the counter 29,

Timing diagrams explaining the principle of operation of the generator 14 are shown in Fig. 7, where 1 is the pulses at the output of frequency divider 30; 2 - pulses at the first output of the reversing counter 31; 3 - pulses at the second output of the reversible counter 31; 4 pulses on the third output of the reversible counter 31; 5 - pulses at the fourth output of the reversible counter 31; 6 - pulses at the output of the element OR 34; 7 - pulses at the first output of the trigger 36 with a counting input; 8 - impulses nz output element OR 35; 9 - cm pulses at the output of the element And 33.

Generator 14 line scan works as follows.

The generator input receives pulses from the generator 15 output with a frequency of 8 MHz. The frequency divider 30 divides the frequency by 16. From the output of the LG divider, the pulses, which follow the BOO Hz frequency, go to the output of the generator 14, to the input of the And 33 element and to the input reversible counter 31, which, during the first half of the row, operates in the pulse summing mode, and during the second half of the row in the subtraction mode. The mode of operation of the reversible counter 31 is determined by the level of the voltage supplied to the input from the output of the trigger 36 with the counting input. Such a circuit solution allows you to simply generate signals

quenches, which in this case are formed at the fourth output of the reversible counter 31. With the help of the element OR 34 pulses are formed at those moments when

A level O is set at all outputs of the reversing counter 34. On the front of these pulses, trigger 36 is switched with a counting input. In addition, this pulses select the pulses sent to element / 33 to form recording pulses, which are fed from the output of element V 32 to the control input of counter 10. With the help of the element OR 35,

5 sync pulses.

The delay 32 of the delay eliminates the appearance of a short positive pulse in the middle of the line due to the delay of the switching moment of the trigger 36 with the counting input relative to the i / omenta of setting all the outputs of the reversing counter 36 to the zero state. From the first output of the reversible counter, 31 pulses with a frequency of 250 kHz are fed to the synchronization input 5 of the ACP4.

The generator 17 frame scan works as follows.

Pulses with a horizontal scanning frequency are received at its input. Counter 38 has

0 is a conversion factor of 256 and counts the pulses arriving at its input if there is a voltage O at the other input, which comes from the first output of the trigger 42. At the same time, the second

5, the output of the trigger P2 is voltage 1, which is fed to the second inputs of counters 37 and 39 and prohibits their operation. When the counter 38 overflows, a negative voltage drop appears at its second output, a short mm pulse is generated from the courier by means of a differentiating circuit 40 and is fed to the input of the trigger 42. At its first output, level 1 appears, which prohibits operation

5 counter 38, and at the second exit - level. O, which enables the operation of the 37t counter of the counter 39, the Counter 37 has a conversion factor of 3, the Second counter 39 due to the presence of feedback from the eighth output of the decoder 41 to the second input of the trigger 43 has a conversion factor of 7. Thus, counting 56 pulses when scrapping the counter 37 and 39, the trigger 42 again switches and blocks the counting of the pulses by the counter 37 and the counter S; OM 39. This also allows the counter 38 to operate, from the first output of which pulses following the frequency f fcrp / 16 are removed . Using the decoder 41, frame sync pulses are formed. From the second output of the trigger 42, the damping pulses are removed.

Shaper 16 coordinate grid works as follows.

Television screen noflcaefa pulses for displaying coordinate grids are formed using one-shot 43, 44. When a one-shot 43 is received at the second input with logic at the input of positive drops of damping signals, it produces short positive pulses. In addition, the positive level of the blanking signals allows the launch of the one-shot 43 by the decay of the pulses arriving at the first input. From the output of a single-vibrator 43 with logic at the input, the light pulses arrive at element I 45, where they are selected by the signal for damping over the frame.

When a second one-shot 44 with a logic at the input of a positive differential signal for damping over a frame arrives at the second input, it produces a positive pulse with a duration of 50-60 μs.

A positive level of the signal also permits the launch of the one-shot 44 by the decay of pulses arriving at its first input. The output signals of the one-shot 44 are selected by line-quenching signals using element AND 46. The element OR 45 forms a mixture of pulses, illuminated to display two coordinate grids on a television screen. If the device is functioning properly, after the erase mode of information is completed, two vertical lines should be displayed on the television screen, corresponding to the zero level of the input signals.

Claims (1)

Invention Formula A device for recording dynamic processes that contains an initial setup signal conditioner, a control signal conditioner, a recording signal conditioner, the input of which is connected to the first output of an analog-digital converter, a switch, whose information inputs are the first and second information inputs of the device, first control the switch input is connected to the first output of the control signal generator connected to the control input of the first counter and the first control input of the mule A multiplexer whose output is connected to the address input of the RAM, information input and output of which are connected respectively to the second output of the analog-digital converter and the preset input of the second counter, the output of which is connected to the first information input of the first mixer, clock generator, the output of which connected to the input of the horizontal scanning generator, the first output of which is connected to the synchronous analog-digital converter, whose information input is dinene with the switch output, the control input of the analog-digital converter is connected to the second output of the control signal generator, whose information input is connected to the first output of the first counter, the second output of which is connected to the first information input of the multiplexer, the sync input of which is connected to the second output of the horizontal scanning generator , the initial shaper output is connected to the reset input of the driver shaper, the trigger input of which is the start signal The device ska, and the first sync input is connected to the first generator output, vertical scan, the second output of which is connected to the first information input of the grid coordinate generator, the third output to the first information input of the second mixer, the second information input of which is connected to the third output of the horizontal scanning generator, the second the output of which is connected to the clock input of the frame scanning generator, the fourth output of the horizontal scanning generator is connected to the second information input of the former, dinatnoy grid, whose output is connected to second data input of the first mixer, a fifth horizontal oscillator output is connected to the control input of the second counter, wherein. that, in order to simplify the device, it contains a delay unit, the input of which and the second control input of the multiplexer are connected to the output of the recording signal generator, the second information input of the multiplexer is connected to the fourth output of the frame sweep generator, the first output of which is connected to the first control input of the coordinate generator the grid, the second control input of which is connected to the sixth output of the horizontal scanning generator connected to the first control input of the selector, the second control input of which It is connected to the first output of the frame sweep generator, the selector output is connected to the synchronous input of the second counter, the clock input of the selector is connected to the output of the clock generator, the second output of the horizontal sweep generator is connected to the second synchronous input of the control signaling device, the output of the initial setting signal generator is connected to the reset input of the first counter, the second control input of the switch is connected to the third output of the control driver, the third information input of the first second mixer coupled to the output of the second mixer and the output of the first mixer is the output device, the input of which the reset signal is input ypl shaper initial setting signal, the delay unit output is connected to a control input of ope- ratienoy memory. BEHIND 3 And LG em1 Lb ABOUT h f ± iЈ / i Vcsl 0  I Fie.6 1 WillJ JShLJ LLggg yGLLJ J J I # LjT-JT TT-jn.jn jin - rT t Fie.7