SU1401642A1 - Device for synchronizing frame scan with supply frequency - Google Patents

Abstract

The invention relates to television technology. The purpose of the invention is to improve the synchronization accuracy. The device contains a clock rc 1, dividers 2, 3 and 5 frequencies, a phase-sensitive unit 4, a pulse shaper b, counters 7, 8 and 10 pulses, a register 9 and a decoder 11. The frequency sync pulse is adjusted in the device not in phase, but in frequency. When the frequency of the network is constant, there are no periodic adjustments to the frequency of the frame sync pulses in one direction or the other, which increases the synchronization accuracy. The goal is achieved by the introduction of the former 6, the counters 8 and 10, the register 9 and the decoder 11. 1 Il. // at

Description

four

about

O5 4 Yu

The invention relates to television technology and can be used in raster scanned information display devices.

The purpose of the invention is to improve the accuracy of synchronization.

The drawing shows a structural electrical circuit of the device.

The device for synchronization of frame scanning with the power frequency contains the following. Recording of information in register 9, as well as resetting the first 7 and second 8 pulse counters, is carried out on the output pulse of the pulse shaper 6 pulses, i.e. once in a few frames (which is determined the division factor of the third frequency divider 5). This solution eliminates the effect of random noise on the power source (network) by averaging the power frequency. Third divider 5

 generator 1, first 2 and second 3 de-Q frequencies and first counter of 7 pulses have. Frequency stems, phase-sensitive unit 4, the same conversion factor. The second tftiy divider is 5 frequencies, the former 6 is a pulse counter 8, thus, is fixed, the first 7 and second 8 counters control the increment of the pulse duration, the register 9, the third counter 10 imgc with respect to the minimum tolerances and the decoder 11 .my (in the periods of the line scan), which device operates as follows. 15 pa is then used to determine the clock generator 1 generates the moment of reset of the second divider 3 frequencies, pulses, whose frequency is an integer number of times higher than the horizontal scanning frequency. The first frequency splitter 2 divides the clock generator pulses 1 to the horizontal expansion frequency, generates horizontal sync pulses at the output that go to the output, and also to the first input of the second divider 3 frequencies that generate frame sync pulses (XI) at the first output. The XI frequency is synchronized with the power supply frequency 25 by changing the division ratio of the second divider 3 frequency by its initial setting at certain points in time.

20

Thus, the device adjusts the XI frequency not in phase, but in frequency.

The proposed device, unlike the one known at constant network frequency, does not produce periodic CSI frequency adjustments in one direction or the other, which ultimately improves the synchronization accuracy.

Claims (1)

Invention Formula Voltage with power frequency, frequency attenuator, the first input and the first output of which are respectively the outputs of the horizontal and frame sync pulses, the phase-sensitive unit, the input device to synchronize the vertical scan with the frequency of the power, containing 4,30 consecutively connected clock geevfilled, for example, in the form of a trigger generator, the first frequency divider and the second Schmidt and forming rectangular and pulses at the time of crossing the power of a certain threshold level. Impulses generated in this way shared by the third frequency divider 5, of which 35 is the input of the mains voltage, the output pulses of which are formed and the output is connected to the input of the third divider by short pulses by the driver of their 6-frequency, as well as the first pulse counter, pulses, performed, for example, in video that, in order to improve the differentiation of the S-C circuit. Synchronization accuracy was introduced by the cipher. After the beginning of the formation of the personnel, the Q torus, the pulse shaper, as well as the lasting pulse (OIG) and the provision of a pulse counter, register and Its minimum permissible pulse counter duration, connected successively at output of decoder 11, is formed, and the output of the first divider is a partial level, allowing the operation to be connected to the first input of the first counter, the third pulse counter 10, which operates in the mode subtracting and determining the pulse counter 45, the third input of which is the number of lower-case pulses to which it is connected to the second via the decoder to the second the duration of the OIG in relation to the minimum the permissible duration. The overflow pulse from the output of the third pulse counter 10 pulses the initial setting of the second divider 3 frequency, 50 which starts counting the new frame period. The entry of the code in the third counter 10 pulses occurs from register 9 in the absence of a signal from the output of the decoder 11. the house of the second frequency divider, the second input of which is connected to the output of the third pulse counter, the output of the pulse driver is connected to the second inputs of the first counter and register, as well as to the first input of the second counter, the second input of which is connected to the output of the first pulse counter, and the pulse driver input is connected with the release of the third frequency divider. Pa is then used to determine when a second splitter 3 is reset, Thus, the device adjusts the XI frequency not in phase, but in frequency. The proposed device, unlike the one known at constant network frequency, does not produce periodic CSI frequency adjustments in one direction or the other, which ultimately improves the synchronization accuracy. Invention Formula the frequency divider, the first input and the first output of which are respectively the outputs of the horizontal and frame sync pulses, the phase-sensitive unit, the input counter, the first frequency divider and the second The second is a voltage input, and the output is connected to the input of the third frequency divider, as well as the first pulse counter, characterized in that, in order to improve synchronization accuracy, a decoder, pulse driver, and a second pulse counter, the register and the third pulse counter connected in series, with the output of the first frequency divider connected to the first input of the first pulse counter and to the second input of the third pulse counter, the third input of which is connected to the second output through the decoder The second frequency divider, the second input of which is connected to the output of the third pulse counter, the output of the pulse generator is connected to the second inputs of the first counter and register, as well as to the first input of the second counter, the second input of which is connected to the output of the first pulse counter, and the input of the pulse driver is connected to the output of the third frequency divider.