SU1202075A1 - Television synchronizing generator - Google Patents

Description

The invention relates to television technology and can be used in display devices

information.

The purpose of the invention is to expand the functionality by ensuring the formation of pulse sequences for simultaneous interlaced and progressive decomposition with a given number of lines and frames and without changing the frame time.

This allows you to apply the proposed sync generator without any changes in systems combined with standard television systems, and with special types of sweep.

The constancy of the frame time for any type of decomposition simplifies the program of operation of the synchro-generator with the information display device.

Figure 1 shows the structural electrical circuit television. sync generator for the case η = 4, 1 = 3; 2 is the same as a television synchro-generator providing simultaneous interlaced and line-by-line scanning; FIG. 3 is an example of a constructive implementation of a switch, a signal source of a logic level and a pulse counter.

The TV sync generator contains serially connected master oscillator 1, counter 2 times, counter 3 per line, counter 4 lines, counter 5 frames, the outputs of each of the counters are bitwise connected to the inputs of the corresponding decoders 6-9, the switch Yu, the input and output group of which are connected respectively with the second output and the first group the input of the counter 4, and the source 11 of the logic level signals, the first and second group of outputs of which are connected respectively with the second group of inputs of the counter 4 and the group of inputs of the switch torus 10, the control input 12, in addition, the TV sync generator of FIG. 2 further comprises a decoder 13, a counter of 14 lines, a switch 15, a source 16 of logic level signals and a control input ,7, the inputs of the decoder 13 are bitwise connected to the outputs of the counter 14, a switch 15 whose input is connected to the output

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the counter 14, and the group of outputs — with the first group of inputs of the counter 14, the source 16, the first and second group of outputs of which are connected respectively to the second group of inputs of the counter 14 and the input group of the switch 15, and the input of the counter 14 is connected to the input of the counter 4.

The switch 10 (fig.Z) contains 10 elements AND-OR-NOT 18-20, trigger 21 and element-NOT 22. The source 11 signal of the logic levels contains resistors 23 and 24, elements AND-NOT 25-28 with outputs 29- 32 respectively 15 but. Input 33 and output 34 has a counter 4.

Sync generator works as follows.

The pulses of the master oscillator 1 2o enter the series-connected meters 2-5. If, for example, the dividing ratio of the counters is 1: 8: 32: 625: 16 and the frequency of the master oscillator 1 is 8 MHz, then at the end of the counter 3, the double line frequency of 2 £ _p is equal to 31,250 Hz and the output 4 rows counter - £ _frame equal to 50 Hz. These frequencies correspond to the standard decomposition of 625 lines per frame at 25 frames per second. Decoders 6-9 provide the formation of various signals and cycles in accordance with the specified frequencies and durations.

The operation of the switch 10 is as follows.

The input 33 of the counter 4 lines receives a double line frequency of 2 £ _p . A count of 4 lines counts the pulses to overflow, after which the leading edge of the overflow pulse from output 34 enters the pre-recording input From the 4-line counter and records the code of the initial state of the 4-line counter specified by the state of trigger 21 via AND-OR elements 18-20 at the information 'inputs ϋ1, P2, 4 and ϋδ of the 4-row counter for the "Line-by-line decomposition" (PR) mode. The trigger 21 is controlled by the input with a falling edge of the overflow pulse from the output 34 of the 4-row counter.

On the control input 12 to the input

source 11 logic levels receive a potential signal "1"

(OL mode) or "0" (mode "Cheres1202075

four

string decomposition "- CR), therefore, at outputs 29 and 32, a logical level" 0 "is produced, and at outputs 30. and 31 - logical" 1 "for PR mode or at outputs 29 and 32 - logical" 1 ", and at outputs 30 and 31 logical "0" for the CR mode, respectively,

With "using the switch 10, it is possible to record the specified code of the initial state of the 4-row counter,

The table shows an example of the initial state code for a 12-bit counter of 4 rows. .

For the PR mode, the 4-row counter from its initial state of 3470 or 3472 (determined by the state of the trigger 21) counts 626 or 624 pulses of 2 £ _st p, which corresponds to 312 and 313 lines of decomposition in each frame of the image.

Thus, if in even frames (2,4,6, etc.) images are displayed 312 lines, then in odd frames (1,3,5, etc.) images are displayed 313 lines, and in this case from - for an integer number of lines, the lines in both frames are drawn superimposed on each other, thereby providing a delayed decomposition with a frame sweep period equal in this case to 20 ms or £ _kaAr =

= 50 Hz. It should be noted that the 313rd line will be displayed at a frequency of 25 Hz, but this does not affect the image quality, since the lines at the beginning and end of the frame are canceled by blanking pulses.

For the CR mode, the counter is 4 lines

from its initial state

3471 regardless of state

trigger 21 due to blocking elements 18-20 at input 30 of switch 10 counts 625 pulses 2 £ _p , which corresponds to 312.5 lines of decomposition in the frame (half-frame) of the image. Thus, both in the even and in the odd frame (half frame) of the image, the same number of lines is displayed - 312.5, and in this case 1/2 of the line plus 312 lines of the same frame

15 (half-frames) are drawn between the lines of another frame (half-frame), thereby providing interlaced decomposition with a period of cadre times

. a twirl, which is also in this case 20 also 20 ms or £ _kaAr = 50 Hz. '

The operation of the television synchro generator in FIG. 2, which provides a simultaneous interlaced and progressive scan, is analogous, with the potential external signal 12 receiving a potential signal "1" (PR mode) and the potential input signal 0 at the controlled input 17 (CR mode) or ₃₀ turns.

• When using a typical synchronous generator during the transition from CR to PR, the synchronization of the synchronous generator and the complete reorganization of the control processor are required, which is costly due to the high cost of the control processor.

The initial state of the counter 4 lines Code of the initial state of the counter 4 lines Decomposition type Discharge 12 | 11 | 1θ | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 [1 3470 11 0 11 0 0 0 1 1 1 0 Line by line 3471 1 1 0 1 1 0 0 0 1 1. 1 1 Interlaced 3472 1 1.0 11 0 0 10 0 00 Line by line

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Claims (2)

1. A TV SYNCHROGENERATOR containing serially connected master oscillator and η counters, the outputs of each of which are bitwise connected to the inputs of the corresponding η decoders, in order to expand the functionality of the device by ensuring the formation of pulse sequences for line-by-line and interlace decomposition A switch is introduced, the input and group of outputs of which are connected respectively to the second output and the first group of inputs of the 1st counter (ΐ = 1 ..... η), and the source signals of logic levels, the first and second groups of outputs of which are connected respectively to the second group of inputs of the d-th counter and the group of inputs of the switch. 2. The sync generator according to claim 1, that is, so that, in order to ensure the formation of pulse sequences for simultaneous line-by-line and interlaced decomposition, (n + 1) -th counter is entered into it, the input of which is connected to the input of the 1st counter, (n + 1) -th decoder, the inputs of which are bitwise connected to the outputs of the (n + 1) -th counter, the second switch, the input of which is connected to the output of the (n + 1) -th counter , and group of outputs - with the first group of inputs (n + 1) -th counter, and the second source of logic level signals, the first and second group of outputs k torogo connected respectively to a second group of inputs (n + 1) -th counter and a group of inputs of the second switch. 1202075 > one