SU1674395A1 - Multiprogrammable television information transfer system - Google Patents

Abstract

The invention relates to a television technique and can be used to transmit multiple unsynchronized television signals over a single channel. The purpose of the invention is to enhance the functionality by providing transmission from unsynchronized sources. This is provided by transmitting signals from switches 4 through blocks 3 to form an ordered sequence of signals, each of which contains an address counter 5, frame sync selector 6, signal information part selector 7, recording resolution signal generation unit 8, and memory block 9 through a video amplifier the mixer 12 to the input of the transmitter 13. The system also contains a block 2 for setting the read sequence, a generator 1 of clock pulses, a counter of 10 pulses, and a source code generator 11. The system of clause 2 of the file is distinguished by the execution of block 3. 1c. f-ly, 2 ill.

Description

The invention relates to a television technique and can be used to transmit multiple unsynchronized television signals over a single channel.

The purpose of the invention is to enhance the functionality by providing transmission from unsynchronized sources.

FIG. 1 shows a block diagram of a multi-program television information transmission system; 2 shows timing diagrams for its operation.

The multiprogramme system for transmitting television information (Fig. 1) contains a generator 1 of clock pulses, a block 2 for setting the reading priority, the first

3.1, the second 3.2 and the third 3.3 blocks the formation of an ordered sequence of signals, the first 4.1, the second 4.2 and the third 4.3 switches, the counter 5 addresses, selector 6 HR sync pulses, the selector 7 information part of the signal, block 8 the formation of the recording resolution signal, block 9 memory, pulse counter 10, source code driver 11, video amplifier-mixer 12, transmitter 13.

Multi-program transmission system of television information works as follows.

The generator 1 generates a standard set of clock pulses. From the output of the generator 1, the frame synchronizing pulses (Fig. 2.a) are fed to the input of the read sequencing unit 2. WITH

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the arrival of the first personnel pulse at the first output of block 2 establishes the level of logic 1 (Fig. 2, b), and at the second and third outputs - the level of logical zero. The front of the second and third frame pulses on the second and third outputs of block 2, respectively, are set to logical 1 levels, and on the other two inputs the levels of logical 0 (Fig. 2, e, g). With the arrival of the fourth frame clock pulse, the control cycle repeats.

The information inputs of the first 4.1, second 4.2, and third 4.3 switches receive information from independent external signal sources. With the falling edge of the pulse generated at the output of block 2, the counter 5 of addresses changes the code pattern at its output, which connects the next information input of switch 4 to its direct and inverse outputs. From the inverse output of the switch 4, the signal enters the input of the selector 6 of frame sync pulses, in which the sync mixture is selected from the full signal and the frame sync pulses are selected (Fig. 2c), which are fed to the counting input of the recording resolution generation unit 8. The information input of block 8 receives a signal from the first output of block 2. When logical information 1 appears at the information input of block 8, it is rewritten to its output by frame sync pulses affecting its counting input. The same happens with logical O. Thus, at the output of block 8 a pulse is generated in phase and duration, which coincides with the frame of the information television signal present at the output of switch 4 (figure 2, d). The signal from the output of block 8 PPC.LRMSTUYT The first input of the memory block 9 and the logic level 1 allow recording of the signal information part, which is selected by the selector 7 of the information signal part from the direct output of the switch 4 and is fed to the information input of the memory block 9. Information is read when a positive level is applied to the input of block 9, which is formed at the output of block 2 (Fig. 2, g). The information from block 9 (Fig. 2, d) is fed to the input of the video amplifier-mixer 12. Similarly, the second 3.2 and third 3.3 blocks form an ordered signal sequence with the only difference that the time shift on the first and second control inputs The second 3.2 and third 3.3 blocks form an ordered sequence of signals relative to the first 3.1 and are 40 and 80 ms, respectively (Figures 2, b, e, g).

The signals of the outputs of the second 3.2 (Fig. 2, h) and the third 3.3 (Fig. 2, and) blocks of formation of an ordered sequence of signals also arrive at the inputs of the video amplifier mixer 12, to the first input of which the first output of the generator 1 receives a sync mixture (Fig. 2, and).

From the third output of block 2, a sequence of pulses is fed to the input of a counter. 10 pulses, the counting coefficient of which is 3 /, when a 10.3 / pulse arrives at the input, a signal appears at the output of the counter, which is fed to the input of shaper 11 of the source code, the output of which is connected to the input of the video amplifier-mixer 12.

Video amplifier-mixer 12 forms a complete TV signal (Fig. 2, L), which is fed to the input of transmitter 13.

Claims (2)

1. Multiprogramming system for transmitting television information, containing the first switch, serially connected clock generator, video amplifier-mixer and transmitter, as well as serially connected pulse counter and shaper source code, the output of which is connected to the second input of video amplifier mixer, about m and h so that, in order to extend the functionality by providing transmission from unsynchronized sources, the second and third switches are introduced into it, the first a swarm and a third block forming an ordered sequence of signals, the first and second inputs of each of which are connected respectively to the first and second information outputs of the same-name switches; the first output — with the control input of the same switch; and the second output — with the corresponding input of the mixer mixer, as well as the read sequencer, whose input is connected to the second output of the clock generator; the first, second, and third outputs are connected to the third inputs of the first , the second and third blocks of the formation of an ordered sequence of signals, respectively, with the first and second outputs of the read sequence setting block connected to the fourth inputs, respectively, of the second third blocks forming an ordered sequence of signals, and the third output - is connected to the fourth the input of the first block of formation of an ordered sequence of signals and g the input of the pulse counter 2. The device is distinguished by the fact that the block for generating an ordered signal sequence contains serially connected frame sync selector pulses, a block for generating a recording resolution signal and a memory block, as well as an address counter and a selector for the information part of the signal whose output is connected to the second input the memory unit whose third input combines pins with the input of the address counter, while the input of the HR sync selector, the input of the information signal part selector, the second input of the write enable signal formation unit, the address counter input, the output of the address counter and the memory block output are respectively the first, second, third and fourth outputs and the first and second inputs of the block forming an ordered sequence of signals but 5} 3 JTL J laLJifi Jil iol