SU940315A1 - Frequency divider with variable countdown ratio - Google Patents

Description

The invention relates to a pulse technique. The frequency depict with fractional dividers, a variable frequency divider, adders, the cpaBHes element or codes, and the quantized delay unit 1 are known. The disadvantages of the divider are its complexity and insufficient operational efficiency. The closest in technical essence to the present invention is a frequency divider containing a frequency division block with a variable delNIN coefficient, a parallel register, whose recording permission is connected to the recording resolution bus, and a serial register whose clock and information inputs are connected respectively to the clock and information , and the outputs are connected to the information register of the parallel register, the outputs of which are connected to the inputs of the frequency block with a variable division factor C2 D. This divider does not provide an adequate range of changes in the division ratio. The purpose of the invention is to expand imane zone of changes in the division ratio. The goal is achieved by the fact that a variable-division pulse frequency divider containing a frequency divider with a controlled division factor, whose information input is connected to the input bus, and the control inputs are connected to the outputs of the parallel register, the first input of which is connected to the resolution enable signal , and the rest of the inputs are connected to the outputs of a serial register, the first input of which is connected to the clock clock bus, an AND element is entered: the OR element, the first input of which is connected nen information signal to the bus, a second input connected to the output of the AND and an output coupled to a second input

the serial register, the last output of which is connected to the first input of the element I, the second input of which is connected to the control signal bus, and the first output of the serial register is connected to the additional control of the frequency divider with the controlled division factor.

The drawing shows the structural electrical circuit of the proposed divider.

The frequency divider contains a frequency divider 1 with a controlled division factor, a parallel register 2, a serial register 3, an AND 4 and

element OR 5. An input signal is fed to the input bus 6, a resolution signal is sent to bus 7, a clock signal is sent to bus 8, an information signal is sent to bus 9, and a control signal is sent to bus 10.

The output signal is removed from the output-, yes 11.

The divider works as follows.

In the frequency division mode, bus 8 receives a reference frequency pulse at the input of register 3, which is numerically equal to the output frequency of the divider.

In register 2, the code of the integer part of the division factor K is written. Register 3 contains a binary sequence corresponding to the fractional part of the division factor I // // A. where Mdl decimal fraction is 10 (see table).

ABOUT

about about about 1

one

Oh oh

about 1 about about 1 about 1

1 1 1 1 1 1 1 1

about.

about

91 1 O 1 1

about

about

one

one

1 On the U divider bus, there is a signal allowing the entry of information from the corresponding output of register 3 to its information input via AND and OR elements. Each reference-frequency pulse, arriving at the register clock input, closed into the ring, shifts the code entered into it by one bit. At the same time, if there is a logical unit in the first bit of register 3, from its output to the auxiliary input of the divider 1 the signal is received, the measurements are ush: the dividing factor of the block 1 is from K. to K + 1. In the case of the future, the division factor remains equal to K. As a result, out of ten periods of the reference frequency, during the Vi-periods, the division factor of the 1 frequency divider is K + 1, and in the 1O-I period, about о о о о 1 1 1 1

about oh. about 1 about 1 1 1 1

oh oh oh 1 oh oh 1

about about 1 about 1 about 1 1 1

about 1 about 1 about 1 about 1 1 coefficient K. This corresponds to the mode of operation of the frequency divider with the fractional division coefficient. When a decision is made to change the division ratio per bus 1O, a logical level prohibits the flow of information through AND and OR elements from the output to the input of the sequential register. Over a period of 10 periods of the clock frequency, the code of the integer part of the division factor is entered into register 3, then it is copied into a parallel register with a signal coming through bus 7. After this period of 10 onopi frequency, the register 3 is filled with a serial code corresponding to the fractional part of the division factor, and then in register 3 is closed in a ring by a signal received via bus 10.

Claims (2)

The claims, the input of which is connected to the bus of the write enable signal, and the remaining inputs are connected to the outputs of the serial register, the first input of which is connected 5 to the bus of the clock signal, characterized in that, in order to expand the range of variation of the division coefficient, an And element and an element are introduced into it OR, the first input of which soe10 of the connections to the bus of the information signal, a second input connected to the output element and _h ment, and an output coupled to the second input sequentially, the register, the latter output is connected to a per15 th input AND gate, a second input coupled to a bus control signal, and the first serial output register connected to the additional control input of the frequency divider 20 with a controlled division ratio. Pulse frequency divider., With a variable division ratio, containing a frequency divider with a controlled division ratio, the information input of which is connected to the input bus, and the control inputs are connected to the outputs of the parallel register, the first 2 $