SU744948A1 - Pulse delay device - Google Patents

Description

(54) DEVICE FOR DELAYING PULSES

one

The invention relates to the field of radio engineering and can be used for controlled digital delay of pulse signals from radio engineering devices, as well as for converting a code into a time interval.

Known devices digital delay pulse signals and converters code-time interval.

One of the known digital delay devices comprises a clock generator, a match element, a work counter, a reference element, a control counter, a trigger, and a key. The input pulse overturns the trigger, which permits the arrival of pulses from the clock generator through the coincidence element to the work counter. When the contents of the counters are equal, the comparison element generates an output signal that sets the working counter to the zero state and the trigger to its initial state and opens the key for supplying a signal allowing the recording of information to the control counter 1.

However, in this digital delay device, it is necessary to use two counters and a multi-input reference element.

which complicates the device. There is also a delay setting error, depending on the recorded number in the control counter, due to the different response times of the working counter triggers. The response speed is understandable, since the comparison temperature is connected in series to the installation and reset circuits. The possibility of using meters with synchronous installation is excluded.

A code-time interval 2 converter is known. It contains a clock generator, a match element, a counter, a reference element, a key, recording gates and a register.

Known transducer code-time interval works as follows.

The input signal, which arrives synchronously with the frequency of the clock generator, transfers the key to a state that permits the passage of pulses from the clock generator to the counter and prohibits the recording of information to the counter from the register through the recording gates. In this case, the counter begins to work in counting mode. Upon completion of the formation of the time interval, the control element generates a pulse at the end of the time interval, which closes the key, stopping the arrival of the pulses from the clock frequency generator through the coincidence element at the counter input and allowing the information to be written to the counter.

However, due to the fact that the end of the interval signal corresponding to a certain counter state passes the comparison element and the key to control the recording gates sequentially, the maximum start frequency of the converter is reduced by a code-time interval, which is determined by the speed of the counter with the recording gates and time distribution of the recording control signal from the counter to the recording gates.

The aim of the invention is to increase the speed of a digital delay device of a pulse signal.

This goal is achieved due to the fact that a pulse delay device containing a serially connected clock generator, a matching element, a counter, a code comparison element, a register connected to the counter input, a key, whose output is connected to the second input of the matching element, an additional coincidence element is introduced, the output of which is connected to the second key input, and its inputs are separately connected to the key output, the second output of the clock generator and the output of the element with Equals, the latter being combined with the output of the low-order bit of the counter and connected to the second input of the meter recording gates.

The drawing shows a functional diagram of a device for delaying pulses.

The proposed device comprises a clock pulse generator 1, a match element 2, a counter 3, a comparison element 4, a switch 5, a recording gate 6, a register 7, and an additional match element 8.

The proposed device works as follows.

The input pulse arrives at key 5, which opens elements 2 and 8 of the match. In these elements, the clock pulses from the generator 1 arrive at the corresponding phase. Through the coincidence element 2, these pulses go to counter 3, which operates in the counting mode until

as long as the signal corresponding to a certain state of the leading bits (for example, all zeros), at the output of the comparison element 4 does not coincide with the output signal of the least significant bit of the counter. At the time of coincidence

These signals through the valves 6 records in the counter 3 is recorded code from the register 7. Simultaneously with the recording of the code in the counter 3 pulse from the generator 1 clock frequency, which coincided with the output pulse of the comparison element 4, passes through the element 8

matches and switches the key 5, which locks the elements 2 and 8 of the match.

A positive effect is achieved due to the fact that the influence of the signal propagation time in the comparison element and the key on the maximum achievable starting frequency of the proposed delay device is excluded. The transition of the counter from the counting mode to the recording mode is determined only by the speed of the meter itself and the recording gates. In this case, the key is in parallel with the recording of information in the counter.

Claims (2)

Invention Formula A device for delaying pulses comprising a serially connected clock generator, a coincidence element, a counter, a code comparison element, connected through recording gates to the counter input register, key, the output of which is connected to the second input of the coincidence element, characterized in that, in order to increase speed, an additional matching element is inserted in it, the output of which is connected to the second input of the key, and its inputs are separately connected with the output of the key, the second output of the clock pulse generator, and the output of the reference element, the latter being combined with the output of the low-order bit of the counter and connected to the second input of the recording gates. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 457158, cl. H 03 H 9/30, 25.02.72. 2. USSR author's certificate No. 323788, cl. G About J 3/00, H 03 K 13/04, 12/31/68 (prototype).