SU527826A1

SU527826A1 - Variable division ratio divider

Info

Publication number: SU527826A1
Application number: SU2130792A
Authority: SU
Inventors: Евгений Семенович Заводий; Анатолий Дмитриевич Подлиннов; Александр Васильевич Шанин
Original assignee: Предприятие П/Я М-5068
Priority date: 1975-05-04
Filing date: 1975-05-04
Publication date: 1976-09-05

Description

1one

Изобретение относитс к радкокзмерительной технике, предназначаетс дл использовани в цифровых cifflTesaTopax частоты радиопередающих и радиоприемных устройств Известен делитель с переменным коэффицентом делени , содержащий счетчик-де- лителЬ) состо щий из информапионного и буферного регистров, вход которого подключен к генератору эталонных сигналов, установочные входы - к выходам вентилей ввода коэффициента делени а выходы триггеров информационного регистра счетчикаделител объединены и через блок с шхро- низации подключены ко входам вентилейSUBSTANCE: invention relates to a radio-measuring technique, is intended for use in digital cifflTesaTopax frequencies of radio transmitting and radio receiving devices. A divider with a variable division factor, containing a counter-divider), consisting of information and buffer registers, the input of which is connected to the reference signal generator, is known, the input inputs are to the outputs of the dividing coefficient input valves and the outputs of the triggers of the information register of the separator counter are combined and connected to the input s gates

ввода коэффициента делени .input division factor.

Однако управление делителем с переменным коэффициентом делени дополнительным кодом управл ющего числа требует дополнительного преобразовани коэффициента делени в дополнительный код, что значительно понижает частоту ввода коэффициента делени , а следовательно и скорость делени .However, the management of a divider with a variable division factor with an additional control number code requires additional conversion of the division factor into an additional code, which significantly reduces the frequency of input of the division factor, and hence the division rate.

Цель изобретени - повышение скорости делени .The purpose of the invention is to increase the rate of division.

В предлагаемый делитель ввело:; нивертор выход которого подключен ко входу первого вентил ввода коэффициента делешх , выход которого пэдклгочел к eдlшичнo ly входу первого триггера пнформацлоипогэ регистра счетчика-делител .In the proposed divider introduced :; The output of the niverter is connected to the input of the first input valve of the coefficient of dash, the output of which is padkloche to the edly ly input of the first trigger of the pnformatlologepoge register of the counter divider.

На чертеже и|:едст,:.5ле;;а структурна схема устройства.In the drawing and |: edst,:. 5le ;; a block diagram of the device.

Делитель с дер;-к;:т енератор эталолных :i шyльcQB 1 счетчш -делитель 2, вентили ввода коэффициента делени 3, блок сш-1хро ннзадии 4; фазовращатель 5 и инвертор 6.The divider with der; -k;: t generator of standard: i shylcQB 1 counting divider 2, the input valves of the division factor 3, the block ssh-1hro nnasadii 4; phase shifter 5 and inverter 6.

Устройство работает следующим образомThe device works as follows

Импульсы с этало.тшого генератора 1 с частотой следовш-и f параллельно поступают на входы п 1риггег)ов буферного регистра и, сдв1шутые на IT фазовращателем 5,-на входы п триггеров гшформацпонногО регистра счетчика- делител 2.The pulses from the reference generator 1 with the frequency of the sequence f in parallel arrive at the inputs n 1 fgg s of the buffer register and, transferred to the IT by the phase shifter 5, to the inputs n of the triggers register of the splitter 2 counter.

Claims

The first impulse received on the triggers of the buffer register rewrites the trigger code of the information register into kick and, having passed through the phase shifter 5, changes the state of the triggers of the 1-register register by one. TaKHvi obrado; :, the reference pulse rewrites the trigger code of the information register into a buffer and increases the trigger code of the information register by one. After counting by the counter-divider 2-2 pulses, the code 0111 ... 1 is set in the trigger register of the information register, i.e. the first trigger is at zero, the rest is one. The next, 1st pulse from generator 1 rewrites code 2 - 2 into the triggers of the buffer register, i.e. opens the pass-through transfer chain and through the phase shifter 5 enters the output of counter-divider 2, the transfer chain, which is an element of coincidence of all units of triggers of the buffer register, except the first one, generates a resolution strobe for introducing the division factor K. An input pulse, synchronized with this gate, opens the input valves 3. The first valve controls a single setup input, the rest with zero triggers of the information register. The division factor in the forward binary code is fed to the device; wherein the first bit of the division factor is supplied to the first input gate through the inverter 6, the rest is directly to the input valves. Since the code state of the informational register triggers is O11 ... 1, the pulse from generator 1 (output) resets only those bits whose gates are controlled by a single potential other than the first bit, i.e., the information register is written to division factor in the reverse code. A unit is recorded in the first bit, if the division factor in it is zero. Thus, the next output pulse appears through. , t, e. each input pulse passes to the output of the device and allows the division factor to be entered into the counter. The time of input of the division factor is rigidly synchronized with the reference input frequency. The present divider allows you to directly set the input division ratio in the forward binary code and thus maximize the input frequency of the division ratio, which is equal to the output frequency of the output signal. The output frequency tuning range is lf (Formula of the Invention A divider with a variable division factor, containing a counter-divider consisting of information and buffer registers, whose input is connected to a generator of reference signals, setting inputs to the outputs of dividing coefficient input gates, and outputs of trigger information signals the register of the delimiter counter is combined and connected through the synchronization unit to the inputs of the dividing coefficient input valves, characterized in that, in order to increase the division rate, into n & An inverter was introduced, the output of which is connected to the input of the first input valve of the fission factor; the output of which is connected to the single input of the first trigger of the information register of the counter-divider. In the examination of the invention, the ed. By 23/34, 1971 (prototype).

Output