SU395839A1 - Digital linear interpolator - Google Patents

Digital linear interpolator

Info

Publication number
SU395839A1
SU395839A1 SU1742603A SU1742603A SU395839A1 SU 395839 A1 SU395839 A1 SU 395839A1 SU 1742603 A SU1742603 A SU 1742603A SU 1742603 A SU1742603 A SU 1742603A SU 395839 A1 SU395839 A1 SU 395839A1
Authority
SU
USSR - Soviet Union
Prior art keywords
frequency divider
additional
outputs
digital linear
inputs
Prior art date
Application number
SU1742603A
Other languages
Russian (ru)
Inventor
Г. С. Кривулин витель Л. Г. Козлов
Original Assignee
Казахский опытно экспериментальный завод геофизических приборов Казгеофизприбор
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Казахский опытно экспериментальный завод геофизических приборов Казгеофизприбор filed Critical Казахский опытно экспериментальный завод геофизических приборов Казгеофизприбор
Priority to SU1742603A priority Critical patent/SU395839A1/en
Application granted granted Critical
Publication of SU395839A1 publication Critical patent/SU395839A1/en

Links

Description

one
The invention relates to the automation of controlling the contour movement of machine tools or drawing machines and is intended for use in digital software control systems.
Digital linear interpolators are known, containing a pulse generator, registers of coordinate increments, each of which bit positions are connected to the first inputs of logical elements “And, the second inputs of elements“ And are connected to the outputs of the corresponding bits of the binary frequency divider, and outputs of the elements “And are connected to the input of the corresponding logical element “OR. Such devices have low speed.
The proposed device differs from the known ones in that it contains a recording circuit and an additional binary frequency divider, the counting input of which is connected to the output of the pulse generator, the output is connected to the input of the binary frequency divider and to the input of the recording circuit, the second inputs of which are connected to the corresponding outputs of the coordinate increment registers , and the outputs are connected to the installation inputs of the additional binary frequency divider. Such a construction device allows to increase its speed.
The drawing shows a block diagram of the device.
The device contains a coordinate increment register / along the X axis, a coordinate register increment 2 along the Y axis, a binary frequency divider 3, a pulse generator 4, an additional frequency divider 5, logic circuits "AND 6, logic circuits" OR 7, and a recording circuit 8.
The interpolator works as follows.
The registers / and 2 bring increments of A and Y, for example from a computer. From the generator 4, the pulses arrive at an additional frequency division 5. By the overflow pulse of the additional frequency divider, a larger coordinate increment from the corresponding register is entered into the additional code in the additional code 8.
In this case, the division factor of the additional divider is, where; V is the magnitude of N + I
on a larger coordinate increment. Overflow pulses with extra
the divider 5 is also fed to the frequency divider 3 and through the logical "And 6" are issued in an amount proportional to the weight of the divider 3, to the "OR 7" circuits from which they are sent to the control channel. The frequency of the pulses in the control channel corresponding to a larger increment is (L + 1) 2 "- 12" - 1 where fr is the frequency of the pulse generator, n is the number of bits of the binary dividers, i.e. the frequency of the pulses in the control channel does not depend on increment values. The registers are set to zero by an overflow pulse from frequency divider 3. The invented digital linear interpolator contains a pulse generator, coordinate registers of 15 datum increments, bit buses each of which are connected to the first inputs of 5 10 logical elements "And the second inputs of elements "And connected to the outputs of the corresponding bits of the binary frequency divider, and the outputs of the elements" AND connected to the input of the corresponding logic element "OR, characterized in that, in order to improve speed, holds the recording circuit and the additional binary frequency divider, the counting input of which is connected to the output of the pulse generator, the output is connected to the input of the binary frequency divider and to the input of the recording circuit, the second inputs of which are connected to the corresponding outputs of the coordinate registers, and the outputs are connected to the installation inputs of the additional binary frequency divider.
AU
SU1742603A 1972-01-24 1972-01-24 Digital linear interpolator SU395839A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU1742603A SU395839A1 (en) 1972-01-24 1972-01-24 Digital linear interpolator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU1742603A SU395839A1 (en) 1972-01-24 1972-01-24 Digital linear interpolator

Publications (1)

Publication Number Publication Date
SU395839A1 true SU395839A1 (en) 1973-08-28

Family

ID=20501569

Family Applications (1)

Application Number Title Priority Date Filing Date
SU1742603A SU395839A1 (en) 1972-01-24 1972-01-24 Digital linear interpolator

Country Status (1)

Country Link
SU (1) SU395839A1 (en)

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