SU1109743A1 - Device for computing polynomial of second order - Google Patents

Abstract

1. A device for calculating a second degree polynomial containing the first and second shift registers, an adder, two AND elements, an OR element, a delay element, a trigger, a synchronization unit, the inverse output of the trigger being connected to the first input of the first And element, the second input of which is connected to the output of the OR element, the first input of which is connected via the delay element, to the direct output of the trigger, the output of the second shift register is connected to the second input of the OR element and the reset input of the trigger, the output of the first AND element is connected to the shift input and the second shift register, the output of the first shift register is connected to the input of the first operand of the adder, the output of which is connected to the shift input of the first shift register, the first input of the synchronization unit is connected to the synchronization inputs of the first and second shift registers, the reset inputs of which are connected to the second output of the synchronization unit, the third input of which is connected to the first input of the second element I, characterized in that, in order to reduce the volume of the equipment, two pulse formers are introduced into it, two pulse taps The second and third elements OR, the third, fourth and fifth elements AND, the element NOT, the delay element, the fourth output of the synchronization unit connected to the control inputs of the first and second pulse shapers, the information inputs of which are connected respectively to the first and second information inputs device, the output of the first pulse generator is connected to the first inputs of the second element OR and the third element AND, the second inputs of which are connected to you (L by the second pulse driver, the outputs of the second the OR element and the third element And are connected respectively to the control inputs of the first and second pulse drivers, the information inputs of the first and second pulse drivers are connected to the fifth output of the synso and timing unit, the output of the second shift register is connected via the second delay element to the first input of the fourth O9 element And, the second input of the fourth element And is connected to the second input of the second element And, to the input of the element NOT and the first output of the second pulse clock, the second output of which is connected to and information input of the trigger, the output of the first pulse clock is connected to the first input of the fifth AND element, the output of which is connected to the first input of the third OR element, the second and third inputs of which are connected respectively to the second and even outputs

Description

And, the output of the OR element is connected to the input of the second rand adder, the second and third inputs of the fifth And element are connected respectively to the output of the element and the output of the second shift register. 2. The device according to claim 1, characterized in that the pulse clock contains two AND-NOT elements. the OR element, two NOT elements, the information input of the pulse clock is connected to the fifth input of the OR element and the first 43 input of the first NAND element, the output of which is connected via the first element NOT to the second pulse clock Vicode, which is connected to the output of the second element NAND and the second input of the first NAND element, the output of which is connected to the first input of the second element NAND, the second input of which is connected to the output of the OR element, the second input of which is SORCHENEN with the output of the second element IRE, whose input is Inonii a control input taktovatel pulses.

one

The invention relates to automation and computer technology and is intended to be squared or to multiply two quantities represented in a digital or analog form of information representation.

Known quadrator containing two shift registers, an adder, two delay elements, a trigger, two OR elements and an AND element).

The lack of such a device is limited functionality, since it does not allow multiplication of two quantities presented in a digital or analog form of information representation.

Closest to the proposed technical entity is a device for calculating a second-degree polynomial containing the first and second shift registers, an adder, two AND elements, an OR element, a delay element, a trigger, a synchronization unit, and the inverse trigger output is connected to the first. And element, the second input of which is connected to the output of the OR element, the first input of which is connected through the delay element to the direct output of the trigger, the output of the second shift register is connected to the second input of the OR element and the reset input sa trigger, the output of the first element And is connected to the shift input of the second shift register, the output of the first shift register is connected to the input of the first operand of the adder, the output of which is connected to the shift input of the first shift register, the first output of the synchronization unit is connected to the clock inputs of the first and second shift registers, the reset inputs of which are connected to the second output of the synchronization unit, the third output of which is connected to the first input of the second element I 2.

A disadvantage of the known device is a large amount of equipment.

The purpose of the invention is to reduce the amount of equipment.

The goal is achieved by the fact that the device containing the first and second shift registers, an adder, two AND elements, an OR element, a delay element, a trigger, a synchronization unit, the inverse trigger output is connected to the first input of the first AND element, the second input of which is connected to the output of the OR element, the first input of which is connected through the delay element to the direct output of the trigger, the output of the second shift register is connected to the second input of the OR element and the reset input of the trigger, the output of the first AND element is connected to the shift input of the second th shift register of the first shift register output is connected to the input of the first adder operand whose output is connected to the input of the first shift shift 1egistra, a first output connected to the synchronization unit inputs the synchronization of the first and second shift registers, the reset inputs of which are connected to the second

the output of the synchronization unit, the third output of which is connected to the first input of the second element AND, two pulse makers, two pulse clock, the second and third 5 elements OR, the third, fourth and fifth elements AND, the element NOT, the delay element, and the fourth output of the block synchronization is connected to the control inputs of the first and second pulse shaper, whose information inputs are connected to the first and second information inputs of the device, respectively, the output of the first pulse shaper is connected to the first inputs of the second element OR and the third element AND, the second inputs of which are connected to the output of the second pulse shaper, the outputs of the second element OR, and the third element 20 AND are connected respectively to the control inputs of the first and second pulse watchers, the information inputs of the first and the second pulse clock is connected to the fifth output of 30-34,

the synchronization block house, the output of the second shift register is connected via the second delay element to the first input of the fourth element I, the second input of the fourth element I is connected to the second input of the second element I, to the input of the element NOT and the first output of the second pulse clock, the second code of which is connected to the information the trigger input, the output of the first pulse clock is connected to the first input of the fifth AND element, the output of which is connected to the first input of the third OR element, the second and third inputs of which are connected respectively venno to the outputs of the second and fourth AND gates, the output OR gate. connected to the input of the second operand of the adder, the second and third inputs of the fifth element And are connected respectively to the output of the element NOT and the output of the second shift register.

In addition, the pulse clock contains two AND-NOT elements, the ORI element has two NOT elements, and the information input of the pulse clock is connected to the first, the input of the SH and the first input of the first AND-NOT element, the output of which is connected through the first element to the second clock output. pulses, the first output of which is connected to the output of the second, the element AND-NOT and the second input of the first element AND-NOT, the output of which is connected to

the first input of the second NAND element, the second input of which is connected to the output of the OR element, the second input of which is connected to the output of the second element NOT, the input of which is connected to the control input of the pulse clock,

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a synchronization unit and pulse clock.

The device contains the registers 1 and 2 shift, adder 3, trigger 4, elements OR 5-7, elements AND 8-12, elements 13 and 14 of the delay per cycle, the element 15, the block 16 synchronization, clocks 17 and 18 pulses, drivers 19 and 20 pulses, information inputs 21 and 22 devices.

The synchronization unit contains a generator of 23 clock pulses, a distributor of 24 pulses, a generator of 25 single pulses, a trigger 26,

the switches 27 and 28, the element NOT 29, the outputrs 17 and 18 of the pulses contain the elements AND-NOT 35 and 36, the elements NOT 37 and 38, the element OR 39, the information input 40, the control input 41 and the outputs 42 and 43.

The device works as follows

In the initial state, the switch 27 of the synchronization unit 16 connects the generator output 25 of single pulses to the information input of the trigger 26. The clock generator 23 of the synchronization unit 16 generates a sequence of clock pulses, of which n-bit distributor 24 pulses form n pulse sequences of duration 1 / f, period, and shifted one relative to the other at the time, where f is the frequency-clock pulses of the generator 23 clock pulses, n is the number of bits of shift registers 1 and 2. Cote-p utator 28 sends a logical unit signal from the output of the NOT 29 element to the start input, a generator of 25 single pulses, the output of which separates a single pulse from the sequence of the n-th bit of the distributor 24 pulses. The output pulse of the generator 25 single pulses through the switch 27 is fed to the information input of the trigger 26, setting it to one state. The signal of the logical unit of the direct output of triple 26 is fed to the inputs of the control of the shift registers 1 and 2, which, under the action of the clock pulses coming from the first output of the synchronization unit 16, are set to the zero state, because logical zero signal. The trigger 4 is set to zero by a zero signal shifted from the output of the shift register 2. Thus, in the initial state, the shift registers 1 and 2, as well as the trigger 4, are in the zero state. The calculation mode is established by the switch 27 by connecting the generator output 25 of single pulses to the start inputs of the drivers 19 and 20 pulses. Calculations to the multiplier quadrant begin after the launch, using the switch 28 of the generator 25 single pulses, the output pulse of which triggers the pulse formers 19 and 20. At the outputs of the formers 19 and 20 pulses, pulses are formed, the duration of which is proportional to the signals (analog or digital) acting on the information inputs 21 and 22 of the device. If the duration of the output pulses of the formers 19 and 20 pulses are different, then the longest pulse is released at the output. of the element OR 7, and a smaller pulse is at the output of the element 12, under the action of which the pulse clock 17 forms a pulse train of 24 times the pulse distributor 24 pulse pulses, the number of which is proportional to the smallest value acting on one of the information inputs 21 and 22 devices, as well as the pulse strobe this batch of pulses. A clock pulse strobe 17 pulses opens AND 9 and 10 elements, and also blocks NOT element I 15 through a pulse element. Pulse output pulse pulse pulse 17 arrives at the trigger information input 4. The first burst pulse sets the trigger state 4 to 1 m tact (corresponding to the shift of the n-th bits of the codes from the outputs of registers 1 and 2 shift). Setting the trigger 4 to one, the state leads to the formation of a zero signal at its inverse output, blocking the AND 8 element, and at the direct output - a single signal that after the delay time of the delay element 13 starts to act through the element OR 5 at the first input element 8. Under the action of .contact pulses of the first output of the synchronization unit 16 from the output of the shift register 2 in the first cycle the lower bit of the initial zero code is shifted, the signal of which goes to the inverse reset of the trigger 4 and sets casts it in the zero position. In the zero state, on the inverse output of the trigger 4, a single signal is generated, which removes the blocking of the IZ element. Due to the delay element 13 of the clock cycle of the direct output signal of the trigger 4 at the input of the element 8, a pulse signal is generated, which in the first TC is recorded as the low-order code in the shift register 2 under the action of the clock pulses of the first output of the synchronization unit 16. During the first clock cycle, the output signal of the first bit of the pulse distributor 24 acting on the third output of the synchronization unit 16 comes through an AND 10 element, opened by the pulse gate output signal of the 17 pulse pulses, and through the OR 6 element, the adder 3 to the information input of the shift register 1. Under the action of the clock pulses of the first output of the synchronization unit 16 in the first clock cycle, a single signal is recorded in the shift register 1 as a low-order bit. During the subsequent clocks from the second to the n-th, the zero bits of the codes from the second to the nth under the action of the clock pulses of the first output of the synchronization unit 16 are copied from the outputs of the shift registers 1 and 2 to their information inputs, and the low-order code moves to the last bit of registers 1 and 2 shift. Thus, after the calculation step, the binary codes of the square function x 1 and the argument X ;, 1 are formed during the clock cycles in the shift register 1 and 2 cooTBetcTBeHHo. In the second and subsequent calculation steps, the smallest pulse signal at the outputs of the formers 19 and 20 pulses in registers 1 and 2, c forms the binary codes of the quadratic function and the argument according to the relation xf XiV2xi., + 1, where Xj and the argument values of the quadratic function at the i and i-1 calculation steps, respectively. For example, setting trigger 4 to the single state by the i-th pulse of a stack acting on the pulse output of the clock 17 pulses ensures that the binary codes of x 2 and X are shifted in registers 1 and the shifts, respectively, according to relation (1) as follows. Under the action of the clock pulses of the first output of the synchronization unit 16 to the first input of the adder 3, the binary code of the X value of the quadratic function is shifted in the previous calculation step, and from the output of the shift register 2 through the delay unit 14, the tacts And 9 or 6 to the second input of the adder 3 are shifted the binary code of the argument x .. The delay element 14 provides a shift by one bit of the binary code x of the argument in the previous step of the assignment with respect to the binary code of the function x, shifted from the output of the register of the 1 shift. The adder 3 is formed according to the relation (1) binary, the code of the quadratic function x; at the i-th computation step, which is sequentially, starting with the least significant bit, is shifted from the output of the adder 3 to the register of the 1st shift. The unit of the youngest row enters from the third output of the synchronization block 16 through the elements AND 10, OR 6 to the second input of the accumulator 3. At this time, in the shift register 2, the binary code of the value x. increases by one. Indeed, the installation of trigger 4 into one state ensures the breaking of the circulation circuit of the codes from the output of shift register 2 to its input, since element 8 is closed by the zero signal of the inverse output of trigger 4. Therefore, until the trigger 4 returns to the zero state the lower bits of the shift register register 2 record zero signals. The trigger 4 returns to the first zero state, starting with the lower bit, the zero code signal, which is shifted from the output of the shift register 2. The transition of the trigger 4 from the single state to the zero state leads to the formation at the output of the element And 8 of a pulse signal due to the delay by the element 13 of the delay of a single signal of the direct output of the trigger 4 of its previous state. Therefore, instead of a zero signal shifted from the output of register 2, a single signal from the output of element 8 arrives at the information input of the shift register 2. The remaining bits of the binary code shifted from the output of shift register 2 are rewritten into shift register 2 without changing through the elements OR 5 and And 8, since trigger 4 is in the zero state. Thus, the binary code in the shift register 2 at each step of the computation increases by one and corresponds to the number of pulses operating at the pulse output of the clock 17 pulses. After the expiration of the smallest pulse at the output of shaper 19 or 20 pulses, element And 12 is closed and. at the outputs of the clock pulse 17, zero signals are set. The zero signal of the gate output of the pulse generator 17 blocks And 9 and 10 elements, and also removes the block Element I 11 through the element NOT 15, at the third input of which the pulse output of the clock pulse 18 continues to operate until the end of the maximum pulse of the generator 19 or 20 pulses. In the time interval from the moment of the end of the smallest to the moment of termination of the largest pulse at the outputs of the formers 19 and 20 pulses, the device implements the operation of multiplying two quantities according to the following relation x-a X, (2) where X is the smallest factor; y is the largest factor. By the end of the smallest pulse (corresponding to the smallest factor), in shift register 1

the binary code X of the smallest co-generator square is formed according to the relation (1), and in the shift register 2 the binary code X of the smallest multiplier is shifted by AND 11 and OR 6 to the second input of the adder 3, where is summed with the binary code of the value x shifted from the output of the shift register 1. The binary code of the sum, starting with the least significant bit, under the action of the clock pulses of the first output of the synchronization unit 16, is recorded in the shift register 1 during the p-cycles.

The formation according to relation (2) proceeds in a similar manner at subsequent steps of the calculations as long as the pulse of the largest factor at the output of the generator 19 or 20 pulses is in effect.

After the termination of the pulse of the largest multiplier at the gate output of the pulse clock 18, a zero signal is set, the blocking element is And 11. Since the elements 9 and 10 are also blocked by the zero signal of the gate output of the pulse clock 17, zero signals act on the second input of the adder 3, and in the register 1, the shift in a dynamic way, by circulating the code through the adder 3, fixes the binary code of the product of the two input values.

In shift register 2, is stored dynamically (by circulating the code through the elements OR 5 and AND 8), the binary code of the smallest factor of the input quantity.

The clock 17 or 18 pulses operates as follows.

The information input 40 receives a sequence of pulses, and the control input 41 receives a control signal.

In the absence of a control signal at the control input 41, the output of the NOT element 38 is set to a signal of a logical unit, coming through the element OR 39 to one of the AND-NOT element 36. In BpeMfi there is a pduza between the pulses at the input 33 at the output of the Y-NO 35 element the signal of the logical unit, which, together with the unit signal of the element OR 39 code, sets the signal of the logical zero to the output of the AND-36 element, blocking the AND-35 element during the action of the pulse at input 33. The signal of the logical unit 1 of the output of the AND-35 element supports ivaet logic zero signal at the output of NOT element 37 '

In the case of a single signal at control input 41, a logic zero signal is set at the output of the NOT element 38. During the pause between the pulses at the input 33 at the output of the element OR 39, a logical zero signal is set, which at the output of the element AND-NOT 36 is a single strobe signal that passes a sequence of pulses of the input 33 through the elements AND-NOT 35 and NOT 37 to the output 42 of the clock 17 pulses. In this mode, during a pulse at input 33, the zero signal at the output of the NAND element 35 blocks the NAND element 36, the output of which supports the signal of the strobe logical unit.

The proposed device can be used in the quadratic function formation mode if the same signal (analog or digital) is fed to the inputs 2 and 22 of the device. If the signals at the inputs 21 and 22 of the device are different, then it forms the binary code of the product of the input quantities.

The use of the proposed device makes it possible to reduce the amount of equipment as compared with the known device.

Claims (2)

1. DEVICE FOR CALCULATING A SECOND DEGREE HALF, containing the first and second shift registers, an adder, two AND elements, an OR element, a delay element, a trigger, a synchronization unit, the trigger inverse output being connected to the first input / output of the first AND element, the second input of which is connected to the output of the OR element, the first input of which is connected through the delay element, with the direct output of the trigger, the output of the second shift register is connected to the second input of the OR element and the reset input of the trigger, the output of the first AND element is connected to the shift input w cerned shift register, the output registers of the first. the shift register is connected to the input of the first operand of the adder, the output of which is connected to the shift input of the first shift register, the first input of the synchronization unit is connected to the sync inputs: the first and second shift registers, the reset inputs of which are connected to the second output of the synchronization unit, the third input of which is connected to the first input of the second element And, characterized in that, in order to reduce the amount of equipment, two pulse shapers, two pulse clocks, the second and third elements OR, the third, fourth and p the element And, the element is NOT, the delay element, and the fourth output of the synchronization unit is connected to the control inputs of the first and second pulse shapers, the information inputs of which are connected respectively to the first and second information inputs of the device, the output of the first pulse shaper is connected to the first inputs of the second OR element and the third element And, the second inputs of which are connected to the output of the second pulse shaper, the outputs of the second element OR and the third element And are connected, respectively, with using the input inputs of the first and second pulse clocks, the information inputs of the first and second pulse clocks are connected to the fifth output of the synchronization unit, the output of the second shift register is connected through the second delay element to the first input of the fourth element And the second input of the fourth element And is connected to the second input of the second element And , with the input of the element NOT and the first output of the second pulse clock, the second output of which is connected to the information input of the trigger, the output of the first pulse clock is connected to the first input of the fifth AND element, the output of which is connected to the first input of the third OR element, the second and third inputs of which are connected respectively to the outputs of the second and even SU ... 1109743 of the yellow AND element, the output of the OR element is connected to the input of the second operand of the adder, the second and third inputs of the fifth element AND are connected respectively to the output of the element NOT and the output of the second shift register. 2. The device pop, 1, characterized in that the pulse clock contains two elements AND NOT. element OR. two elements are NOT. moreover, the information input of the pulse clock is connected to the first input of the OR element and the first input of the first AND-NOT element, the output of which is connected through the first element NOT to the second output of the pulse clock, the first output of which is connected with the output of the second AND-NOT element and the second input the first AND-NOT element, the output of which is connected to the first input of the second AND-NOT element, the second input of which is connected to the output of the OR element, the second input of which is connected to the output of the second element NOT, the input of which is connected to the control input pulse generator.