JPH0126208B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a serial-to-parallel converter that converts bit-serial and channel-parallel signals into a bit-parallel and channel-serial transmission system.

<Prior Art> A circuit block diagram of a conventional two-channel serial-to-parallel converter is shown in FIG. In the figure, reference numeral 1 denotes a two-channel serial signal generator, and the two-channel serial signal generator 1 outputs data in parallel channels and serially outputs bits simultaneously in each channel. The data of each output channel is stored in N-bit register 2 and N-bit register 2, respectively.
Transferred to bit register 3. However, since the transfer to the N-bit register 3 is performed via the shift register 4, it is delayed, and therefore the timing at which N-bit data is held is different between the N-bit register 2 and the N-bit register 3. Bit data is output in parallel to the N-bit latch 5 by switching the switch S to the C side or the D side in synchronization with the timing when N-bit data is held in the N-bit register 2 and N-bit register 3, respectively. Ru. Also, the channels are output serially.
However, the two-channel serial-parallel converter described above requires as many switchers S as there are output bits, and the wiring is complicated, which is disadvantageous.

<Objective> An object of the present invention is to provide a serial-parallel converter with a small number of switches and simple wiring.

<Embodiment> Hereinafter, an embodiment of the serial-parallel converter according to the present invention will be described in detail.

FIG. 2 shows a circuit block diagram of an embodiment of a serial-to-parallel converter according to the present invention. Reference numeral 1 denotes a two-channel serial signal generator, and the two-channel serial signal generator 1 outputs data in parallel channels and serially outputs bits in each channel simultaneously. R ₁ and R ₂ are I-bit shift registers, and R ₃ , R ₄ , and R ₅ are J-bit shift registers. 5 is an N-bit latch circuit. Note that N=I+J. It is assumed that the data of the 2-channel serial signal generator 1 is output in order starting from the LSB. When the data at the output point X of the J-bit shift register R ₄ is LSB, the switches S ₁ and S ₂ are respectively connected to the side. Then I
When the clock is transmitted, the J-bit shift registers _R4 , _R3 and the I-bit shift register are activated.
N bits of data from the ₂ -channel serial signal generator 1 are held in R2 from LSB to MSB. At this time, the bits from J-bit shift register _R3 and I-bit shift register _R2 are N in parallel.
It is taken into Bit Latch H. Next, data is transferred at output point Y of J-bit shift register _R5 .
When it is LSB, the switches S ₁ and S ₂ are respectively connected to the side. Thereafter, when the transmission clock is output by the I clock, N bits of data from the 2-channel serial signal generator 1 are held in the J-bit shift registers R ₅ and R ₃ and the I-bit shift register R ₂ from LSB to MSB. At this time, bits are taken in parallel from the J-bit shift register _R3 and the I-bit shift register _R2 into the N-bit latch 5. By repeating this operation thereafter, a serial-to-parallel converter can be realized using only two switches S ₁ and S ₂ .

FIGS. 3a to 3g are circuit block diagrams for explaining the operation of the above serial-parallel converter for each clock. The same parts as in FIG. 2 are denoted by the same reference numerals, but to simplify the explanation, the data output from the two-channel serial signal generator 1 is assumed to be 4-bit serial data, and the latch 5 is assumed to be a 4-bit latch. The operation will be explained below.

(a)...The first bit data LSB is transmitted from the two-channel serial signal generator 1 (FIG. 3a). 〓 indicates the data of the lower channel.

(b) ...The following data is transmitted (Figure 3b).

( _c ) ...Since _{the first} bit data _LSB has reached point Figure 3(c)).

(d)...The shift register _R3 and the shift register _R2 are filled with data, and the data from MSB to LSB is taken in as parallel bits into the 4-bit latch 5 (FIG. 3(d)).

(e) …first bit data of lower channel
Since the LSB has reached the Y point, the switch S ₁ and S ₂ are connected to the side and the shift register respectively.
The bit data of the lower channel is entered into _R3 and shift register _R2 (Fig. 3(e)).

(f) ...Shift register R ₃ and shift register R ₂ are filled with the data of the lower channel, and the data from MSB to LSB of the lower channel is taken into the 4-bit latch 5 as parallel bits (Fig. 3 (f)). .

(g) ...again, the switches S ₁ and S ₂ are connected side to side, respectively, so that shift register R ₃ and shift register R ₂
The data of the upper channel is entered one bit at a time (Figure 3(g)).

This operation is repeated thereafter.

Although the above embodiments have shown two channels, the present invention is also applicable to three or more channels.

<Effects> According to the present invention, the number of switchers and the number of wires can be reduced, so the area occupied by the wires can be reduced. Therefore, when the serial-parallel converter according to the present invention is implemented as an LSI, there is an advantage that the chip area becomes smaller.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a conventional two-channel serial-to-parallel converter, and FIGS. 2 and 3 are circuit block diagrams of an embodiment of the serial-to-parallel converter according to the present invention. In the figure, 1... 2-channel serial signal generator, 2, 3... N-bit shift register, 4...
Shift register, 5...N bit latch, R ₁ ~
_R6 ...Shift register.

Claims (1)

[Claims] 1 Bit serial and channel parallel signals output from a 2 channel serial signal generator
A serial-to-parallel converter that converts N-bit signals into two bit-parallel and channel-serial N-bit signals, the serial input and serial signal being connected to the first output of the two-channel serial signal generator. a first J-bit shift register of output, a first I-bit shift register (I+J=N) of serial input/serial output connected to the second output of the two-channel serial signal generator; A second J-bit shift register with serial input and serial output is connected to the output of the I-bit shift register of A third J-bit shift register with serial input/parallel output is input, a second I-bit shift register with serial input/parallel output whose output is input to the second part of the N-bit latch circuit, and a second I-bit shift register with serial input/parallel output is input. The inputs to the third J-bit shift register and the second I-bit shift register are input to the third J-bit shift register and the second I-bit shift register at predetermined timing of
Set to the first output of the channel serial signal generator and the output of the first J-bit shift register, and input to the third J-bit shift register and the second I-bit shift register at a second predetermined timing. A serial-to-parallel converter comprising: a switch for setting the output of the first I-bit shift register and the output of the second J-bit shift register.