JPS58213541A - Data separating circuit - Google Patents

Abstract

PURPOSE:To simplify the titled circuit and to change a frame configuration by the change of an ROM data, by using a first in first out (FIFO) memory and an ROM. CONSTITUTION:The data input 417 of 64Kb/s is inputted to the FIFOs 409, 410, 411. The output of a frame counter 403 is supplied to the address input of an ROM407. An output 412 is a pattern indicating the time position on the frame of data of 32Kb/s. Simiarly, the outputs 413, 413 of an ROM407 are also made correspond to the data of 12.8Kb/s and 6.4Kb/s respectively. The outputs of NAND circuits 404, 405, and 406 are connected to a writing clock input and only the data of 32Kb/s, 12.8Kb/s and 6.4Kb/s out of inputs 417 multiplied by the FIFO are written. The clock output 421 of 32kHz from a clock generating circuit 408 is supplied to the FIFO 409, the data of 32Kb/s are read out and data 422 are outputted from the FIFO 409. The same treatment is applied also to the clock outputs 420, 419 of 12.8kHz and 6.4kHz.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data separation circuit that separates time division multiplexed data signals.

First, a conventional data separation circuit will be explained with reference to the drawings.

Referring to FIG. 1, a frame structure of time division multiplexed data, which is an input signal to a data separation circuit, is shown. In Figure 1, A is 64Kb/multiplexed data, B is 1
Frame (20 bits).

- A signal for providing a time reference for time division multiplexing for each system, and in this example, it is a 4-bit fixed pattern.

Referring to FIG. 2, a conventional data separation circuit is shown. As is clear from the frame structure of FIG. 1, the circuit in FIG. 2 receives 64 Kb/s data that has been multiplexed by 9 time divisions, and divides the data into 32 Kb/s data and 12.8 Kb/s data.
This is a data separation circuit that separates data into three types: Kb/s data and 6.4 Kb/s data.

Hereinafter, the operation of the circuit shown in FIG. 2 will be explained with reference to FIG. 6 as well.

The 64 KHz clock input 228 (Fig. 6 ■) is divided by the clock generation circuit 211, and the 32 KHz clock 262 (Fig. 3 ■ I), the 12.8 KH7 clock 266 (Fig. 6 ■), the 6.4 KHz clock (Fig. 6 ■) 234- type B clock pulse.Input 64 Kb/s time division multiplexed data 227
(Fig. 5) is supplied to shift registers 212-217.

At the same time, a 64 Kb/s data input 227 is provided to the synchronization signal detection circuit 201. In the synchronization signal detection circuit 2 old, a synchronization signal indicating the time reference of the nine time division multiplexed frames is detected, and a synchronization signal detection pulse 202 (◎ in FIG. 6) is supplied to the frame synchronization circuit 203. The frame synchronization circuit 206 eliminates the instability of the synchronization signal detection pulse 202 caused by bit errors in the transmission path, and stabilizes the frame pulse 204 (the first Figure 5 ■) is output. The frame counter 205 is driven by a 64KH7 clock input 228, is preset to four states II I 11 by the frame pulse 204, and operates at a cycle equal to the number of bits in one frame (ie, 20 bits). Output of the frame counter 205 (Fig. 6 ■) c.
It is connected to a decoder 206 and a switch switching circuit 207. The decoder 206 receives gate signals (i.e., intra-frame multiplexing time position indicating signals) 229, 230, 231 (
Figure 6 (■, ■, ■) occurs. AND circuit 208
．． 209.210 is.

The decoder output 229.230.231 is ANDed with the 64 KHz clock 228 to generate a burst of 64
It generates a KHz clock. Switch switching circuit 2
07 generates a signal (shown in FIG. 5) for switching the switches 218 to 226 every frame. switch 21
The outputs of 8 to 223 are shown in FIG. 6, O to ■, respectively.

Shift registers 212 and 213 are responsible for separating 32Kb7g of data. That is, switch: 21
When 8.219.224 is in the state of FIG. 2 (the low level state of FIG. 3), the shift register 213 is.

64 Kb/s data input 227 to AND circuit 208
32K with a 64 KHz clock in bursts of output
On the other hand, only the multiplexed time position of b/s data is written.

The shift register 212 has 32K written one frame ago.
b/s data to the output 32 of the clock generation circuit 211.
It is read out using a KHz clock 262. In the next frame, switch 218 .
219 and 224 are switched to the state opposite to that in FIG. 2 (the high level state in FIG. 6), and the operation of the shift register is reversed, so that the shift register 212 performs a write operation and the shift register 216 performs a read operation. . This causes switch 224
In the output 235 of.

32 separate from 64 Kb/s data input 227
KbA data (shown in FIG. 6) is output. A similar operation is performed for 12.8 Kb/s of data, and the output 266 of switch 225 has 12.8 Kb/s of data (
) in FIG. 6 is output. Furthermore, 6.4 Kb
Similarly, for the /s data, separated 6.4 KbA data (n in FIG. 6) is output to the output 237 of the switch 226.

The data separation circuit shown in Figure 2 requires a pair (two) of shift registers for each output data and uses a large number of switch circuits, so the number of integrated circuit chips used is large. There are drawbacks, and when changing the frame configuration, there is the inconvenience that the circuit configuration of the decoder that determines the time position on the frame must be changed.

An object of the present invention is to eliminate the above drawbacks and provide a highly versatile data separation circuit with a simple circuit configuration.

According to this invention, instead of a pair of shift registers corresponding to each output data in the conventional circuit.

First in-first out memory (Fi
rst In First Out Memory (hereinafter abbreviated as FIFO) to simplify the nine circuits, and use a read-only memory (hereinafter abbreviated as ROM) in place of the decoder in the conventional circuit to improve the frame structure. The changes are not changes to the circuit configuration.

This can be easily handled by changing the ROM data. A highly versatile data separation circuit with a simple circuit configuration can be obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 4, a data separation circuit according to an embodiment of the present invention is similar to the circuit shown in FIG.

This realizes the frame configuration shown in FIG.

The operation of the circuit shown in FIG. 4 will be explained below with reference to FIG. 5 as well.

Clock generation circuit 408i'j: 52KHz clock 421 (in Figure 5) corresponding to the clock speed of the output data from the 64KHz clock input 418 (in Figure 5).
.

12.8 KHz clock 420 (Fig. 5 ■), 6.
A 4KHz clock 419 (FIG. 5, ■) is generated. 6
4 Kb/s data power 417 (Fig. 5 ■) is F
It is input as data input of IFO409,410,411. In addition, a synchronizing signal shown simultaneously is detected, and a synchronizing signal detection pulse 415 (■ in FIG. 5) is transmitted to the frame synchronizing circuit 4.
02. The frame synchronization circuit 402U completely eliminates the instability of the Domei signal detection pulse 415 caused by bit errors in the transmission path, and provides a stable frame pulse 416 ( Figure 5 ■) Full output. Frame counter 403 H, driven by a 64 KHz clock input 418, enters state II I by frame pulse 416
It is preset to 11 and operates at the same cycle as the number of bits in one frame (ie, 20 bits). The output of the frame counter 406 ((■) in FIG. 5) is supplied to the at Vs input of the ROM 407. The storage capacity of the ROM 407 is 20 words and 6 bits. ROM40
The output 412 (of FIG. 5) of 7 is a pattern indicating the temporal position on a frame of 32 Kb/s data (i.e., an intraframe multiplexed temporal position indication signal). Similarly, ROM4
The output 416 of ROM 40 (■ in Figure 5) is a pattern indicating the time position on the frame of 12.8 Kb/s data (i.e., an intra-frame multiplexed time position indication signal).
The output 414 of 7 (■ in FIG. 5) is a pattern indicating the time position on the frame of U 6.4 KbA data (ie, an intra-frame multiplex time position indication signal). nand circuit 40
4.405.406 performs the NAND of the outputs 412, 413, 414 of the ROM 407 and the 64 KHz signal 418. Output of NAND circuit 404 (Fig. 5 ■
)teeth.

Connected to the write clock input of FIFO409, FI
64Kb/+ data multiplexed to FO409 4
Of the 17, only the 32KbA data portion is written.

Also, the output of the NAND circuit 405 (Fig. 5 ■) c.

Connected to the write clock input of FIFO410,
F.

Only a 12.8 Kb/data portion of the 64 KbA data 417 multiplexed to 410 is written.

Similarly, the output of the NAND circuit 406 (Fig. 5 ■) is as follows.

Connected to the write clock input of FIFO411, FI
Of the 64 Kb/i+ data input 417 multiplexed to the FO 411, only the 6.4 Kb/i+ data portion can be written.

Clock output 4 of clock generation circuit 408032KHz
21 (in FIG. 5) is supplied to the read clock input of the FIFO 409, 32 Kb/s of data is read out from the FIFO 409, and 32 Kb/s data 422 (FIG. 5 [phase]) separated by 9 is sent to the FIFO 409. It is output from In addition, the 12.8 KHz of the clock generation circuit 408
The clock output 420 (■ in Fig. 5) is the FIFO 41
The data of 12.8 Kb/, which is supplied to the read clock input of 0, is sent out from the FIFO 410, and the data 423 of 12.8 KbA (Fig. 5 ■) which is separated by 9 is sent to the FIFO
Output from O41D. Similarly, clock generation circuit 4
08 6.4KHz clock output 419 (Fig. 5■)
is supplied to the read clock output of FIFO411,
Data of 6.4 Kb/i is sent out from the FIFO 411, and data 424 of 6.4 Kb/s (FIG. 5) separated by nine is outputted from the FIFO 411.

Although the above embodiment is a data separation circuit for six data outputs, generally N FIF9. Use N NAND circuits, make the ROM capacity at least (number of bits in the frame x N) bits,
This can be achieved by changing the number of output clocks of the clock generation circuit to a number corresponding to the type of clock speed of the required output data.

Below, nine detailed explanations of the present invention will be given.

Conventionally, two 77 registers (generally twice the number of storage elements) were required for one output data for data separation, but in the present invention.

Separation is possible by using one FIFO i instead of two shift registers, and with this, the related circuit for switching between the two shift registers (memory elements) is no longer required, simplifying the two circuits and reducing the integrated circuit used. It became possible to reduce the number of chips.

In addition, conventionally, a decoder configured by wired logic was used to determine the data multiplexing time position on a frame, but in the present invention, the number of integrated circuit chips can be reduced by replacing the decoder with a tROM. . Also, conventionally,
This was done by changing the wiring logic of the decoder.

In the present invention, changing the frame configuration such as changing the number of output data, changing the clock speed of the output data, and selecting centralized placement and distributed placement of data within the frame is possible in the present invention.
This can be done easily and quickly by changing the data contents of M.

According to the invention. Simplifying logic circuits using logic integrated circuits and reducing the number of integrated circuit chips used greatly contributes to downsizing equipment, lowering power consumption, reducing inspection man-hours, and lowering costs.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a time division multiplexed frame structure. FIG. 2 is a block diagram of a conventional data separation circuit for realizing the frame configuration of FIG. 1. In FIG. 2, 201 is a synchronization signal detection circuit. 206: frame synchronization circuit, 205U frame counter, 206: decoder, 201j: Suinochi switching circuit, 2
08-2101-1: AND circuit, 211 is a clock generation circuit, 212-217 is a /ft register, 218-2
26 is a changeover switch. FIG. 6 is a timing diagram showing the waveforms of each part in FIG. 2, and the symbols surrounded by black squares have a one-to-one correspondence between FIG. 6 and FIG. 2. FIG. 4 is a block diagram of a data separation circuit according to an embodiment of the present invention. In Fig. 4. 4 old is a synchronization signal detection circuit, 402 is a frame synchronization circuit,
403 is a frame counter, 404 to 406 are NAND circuits, 407 is a ROM, 408il"i clock generation circuit, and 409 to 411 are FIFOs. FIG. 5 is a timing diagram showing waveforms at each part in FIG. The symbols enclosed in parentheses have a one-to-one correspondence between Figures 5 and 4. ■ e Oo ■ [F] ■ ■S00
■■■■■'s O■O■ Figure 4, 5th flash■

Claims (1)

[Claims] 1. In a data separation circuit that separates a plurality of data signals from an input signal including a time division multiplexed data signal, a synchronization signal that detects a synchronization signal that is a time reference for time division multiplexing from the input signal. A detection circuit and receives the output signal of this synchronization signal detection circuit. a frame synchronization circuit that generates a frame pulse having a period of at least one frame; and a frame synchronization circuit whose counting is controlled by the frame pulse and is driven by a first clock pulse having a clock speed of the input signal, and which has a period of at least one frame. A frame counter having a period, and an address input terminal connected to the output terminal of the frame counter,
a read-only memory storing a plurality of intra-frame multiplexed time position indication signals corresponding to the plurality of data signals; a clock generation circuit that generates a second clock pulse; and a clock generation circuit that is arranged in a plurality of stages corresponding to the plurality of data signals, receives the input signal at a data input terminal, and outputs a corresponding intra-frame multiplexing time from the read-only memory. a first-in first-out memory receiving a gated signal of the first clock pulse at a write clock input terminal and a corresponding second clock pulse at a read clock input terminal according to a position indication signal; , a data separation circuit characterized in that the plurality of data signals are separated and outputted to output terminals of the plurality of first-in first-out memories.