SU1758873A1 - Reversible binary counter - Google Patents

Abstract

The invention relates to a pulse and computer technology and can be used in the construction of counting, recording devices, digital information processing systems. The purpose of the invention is to increase reliability. The counter contains a four-bit binary reversible counter 1 and n - 4 cells 2, each of which consists of a counting trigger 4 and a driver 3. The odd-cell driver is made on three AND-NOT elements, the inverter and the IL-N-element, and the even cells are - on the four elements IL AND-NOT. The counter has increased reliability due to the simpler implementation of a four-bit binary reversible counter and cell formers and a new set of links. 3 il.

Description

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The invention relates to a pulse and computer technology and can be used in the construction of counting, recording devices, digital data processing systems,

A reverse binary counter is known, which contains in each bit, except the first, a counting trigger, two AND-NOT / AND elements. the AND-NOT element, and in the first discharge, the deductive trigger and the OR element,

A disadvantage of the known device is the large delay in the operation of the counter. The closest to the proposed solution by the technical nature and accepted as a prototype is a reversible binary counter containing a four-bit binary reversing counter and n - 4 cells, each of which consists of a countable rpni repa and a former.

The disadvantage of the prototype is low reliability.

The purpose of the invention is to increase the reliability of the counter.

The goal is achieved by the fact that in a binary n-bit reversible counter containing a four-bit binary reversing counter and n - 4 cells, each of which consists of a counting trigger and a former, the direct read outputs of the four-bit counter and the forward outputs of counting triggers the cells are connected to the corresponding readout buses of the device, the counting input of the four-bit counter is connected to the input counting signal bus, and its control inputs are connected to the control signals busses of the device; the first inputs of drivers all cells are connected to the overflow output of the four-bit counter the second output of the imager in each cell is connected to the counting trigger input, the second and fifth inputs of the cell imagers, starting with the sixth bit, are connected respectively with the first and third outputs of the former bit generator, the third and fourth the inputs of shapers of even bits, starting from the sixth, are connected to the inverse and direct outputs of the trigger of the previous bit, respectively, the third and fourth inputs of shapers of odd bits, beginning From the seventh, connected to the direct and inverse outputs of the trigger of the previous bit, respectively, the first and third outputs of the former n-th bit generator are connected to the first and second output buses of the device expansion, respectively, the second constructive links are introduced - the second and n shaper inputs

The fifth bit is connected to the first and second buses of the control signals of the device, respectively, the third and fourth inputs of the fifth bit generator are connected to the logical source 1, the even bits, starting from the sixth, contain four elements; and the second inputs of the first and second elements OR are NOT connected to 0, respectively, to the second, third and fourth, and fifth inputs of the driver, respectively, and their outputs to the inputs of the third element OR-NOT and the first and third outputs of the driver, respectively. But the inputs of the fourth element OR are NOT connected to the first input of the imaging unit and the output of the third element OR NOT, and its output to the second output of the imaging device, the generator of each 0 odd bit, starting from the fifth, contains three AND-NOT elements, the element OR-NOT and the inverter, the first and second inputs of the first and second elements AND-NOT are connected respectively to the second, third and fourth, fifth, and fifth inputs of the driver, and their outputs - to the inputs of the third AND-NOT element and the first and third outputs shaper, respectively, the inputs of the element OR- E are connected to the first input of the for- 0 mirovztel and output inverter having an input connected to the output of the third AND-NO element, an output of OR-NO element is connected to the second output of the shaper

5 The proposed device meets the criterion of significant differences. The use of OR-NOT elements in binary reversible counters is well known. However, their use in this device allowed to achieve the effect expressed by the purpose of the invention.

Since the entered constructive connections in similar technical solutions are not known, the device can be considered as 5 having significant differences.

FIG. I shows a binary reversible counter; Fig. 2 illustrates an odd bit driver; FIG. 3 is an even bit driver circuit. 0The binary reversible counter circuit (FIG. 1) contains a four-bit binary reversible counter 1, cells 2s -2n counter, each of which consists of a generator 3 and a counting trigger 4, a counting 5 input C of the counter 1 is connected to the bus 5 of the input counting signals, inputs The counter clock control Ei and E2 are connected to buses 6 and 7 of the control input signals, respectively, the forward read outputs of counter 1 and trigger 4 reads

the device, the overflow output F of the counter 1 is connected to the first inputs of the formers of the 3 cells of the device, the second and fifth inputs of the imaging unit 3 cells 2s are connected to the input buses 6 and 7, respectively, and the third and fourth inputs of the imaging unit 3 of each cell 2i, i 6, .. .n, are connected to the first and third outputs of the generator 3 of the previous cell, respectively, the third and fourth inputs of the generator 3 of each odd cell, starting from 2nd, are connected respectively to the direct and inverse outputs of the trigger 4 of the previous cell, the third and fourth input shaper 3 of each cell, starting from 2o, are connected respectively with inverse and direct outputs of trigger 4 of the previous cell, the second output of shaper 3 in each cell is connected to the counting input of trigger 4 of this cell, the first and third outputs of shaper 3 cells 2P are connected, respectively with the first 9 and second 10 outputs of the expansion device.

The circuit of the odd-sized driver (figure 2) consists of AND-NE 11 - 13 elements, inverter 14 and OR-NOT 15 element, has five inputs 16 - 20 and three outputs 21-23, the inputs of the AND-NE elements 11 and 12 are the second 17 and third 18, fourth 19 and fifth 20 inputs of the former, respectively, and their outputs are the first 21 and third 23 outputs of the former, respectively, and are connected to the inputs of the AND-HE element 13, the output of which through inverter 14 is connected to the second input of the element OR NOT 15, the first input and output of which are, respectively, the first to enter 16 and the second output 22 shapers.

The even bit driver (FIG. 3) consists of OR-NOT elements 24-27, has five inputs 28-32 and three outputs 33-35, the inputs of elements OR-NOT 24 and 25 are respectively inputs 29 and 30, 31 and 32 of the imaging device, and their outputs are with the first 33 and third 35 outputs of the imaging device, respectively, and are connected to the inputs of the OR-NO element 26, the output of which is connected to the second input of the OR-NO element 27, the first input and output of which are respectively the first input 28 and the second output 34 of the former.

The scheme of a binary reversive lock works as follows. On the input bus 5 receives the counting signals. On buses G and 7, account control signals EI and Ea. With EI 1, E2 0 - direct invoice, with EI 0, E2 1 - inverse (for subtraction); with EI E2 0, the account is locked (the counter keeps its state). Combination of Ei - E2 1

is prohibited. At the overflow output F of the counter, a signal is generated.

F C0 (ErQrQ2-Qj-Q4 - E2-QrQ2-Q3-Q4),

P)

where QI -Q4 are readout outputs of counter 1. This signal switches the triggers of the corresponding bits when there are signals on the inputs of the drivers that allow switching of the bit. With this control, the 1st bit trigger input is represented by

Ci Ca- (Ei-Qi ... Qi-i + E2Qi ... QH) (2)

one

provided that the EI E2 combination is prohibited.

Features of this scheme in comparison with the prototype of the following.

Four-bit counter 1 is simpler and more reliable in execution, since the required number of its outputs is two less than in the prototype (5 vs. 7); the odd-bit former contains two elements and one input less than in the prototype; an even bit shaper contains one element and one input less than in the prototype.

Thus, the proposed device has less complexity, and hence greater reliability compared with the prototype. The purpose of the invention has been achieved.

In addition, this binary reversible counter has a better speed compared to the prototype, since the discharge drivers have two times less delay on the first input, which is the trigger switch signal than the prototype drivers on the first and sixth inputs of the same purpose.

As a four-bit reversible counter, any known implementation can be used, having two inputs for controlling the type of counter, which must be supplemented by an overflow output generation circuit F in accordance with formula (1).

Claims (1)

Invention Formula A binary reversible counter containing a four-bit binary reversing counter and n - 4 cells, each of which consists of a counting trigger and a driver, direct read outputs of a four-bit counter and direct outputs of the counting cell trigger points are connected to the corresponding read lines the device, the counting input of the four-bit counter is connected to the bus of the input counting signal, and its control inputs are connected to the buses of the control signals of the device, the first inputs of the drivers of all the cells are connected to the overflow output of the four-bit counter, the second output of the imager in each cell is connected to the counting input the trigger, the second and fifth inputs of the cell formers, starting with the sixth bit, are connected respectively with the first and third outputs of the former bit generator, the third and fourth inputs of the cells the even bits, starting from the sixth, are connected to the inverse and direct outputs of the previous bit trigger, respectively, the third and fourth inputs of the odd bits, starting from the seventh, are connected to the direct and inverse outputs of the previous bit trigger, respectively, The first and third outputs of the former n-th driver are connected to the first and second output expansion buses of the device, respectively, characterized in that. in order to increase the reliability of the counter, the second and fifth inputs of the fifth-bit generator are connected to the first and second buses of the control signals of the vr-array of the corresponding Actually, the third and fourth inputs of the fifth-order driver are connected to the source of logical 1, the even-bit drivers, starting from the sixth, contain four OR-NOT elements, the first and second inputs of the first and second OR-NOT elements are respectively connected to the second, third and the fourth, fifth volume of the driver, respectively, and their outputs to the inputs of the third element OR NOT and the first and third outputs of the driver, respectively, the inputs of the fourth element OR-NOT connected to the first input of the driver and the third output element OR NOT, and its output, with the second output of the driver, the driver of each odd bit, starting from the fifth, contains three AND-NOT elements, the OR-NOT element and the inverter, the first and second inputs of the first and second AND elements They are NOT connected to the second, third and fourth, or fifth inputs of the driver, respectively, and their outputs to the inputs of the third element AND-NOT and the first and third outputs of the driver, respectively, the inputs of the element OR-NOT connected to the first driver of the driver and the output of the inverter, whose input connected to the output t etego AND-NO element, an output of OR-NO element is connected to the second vyhplpm shaper. 1 28 o Fig.Z Jj o J4