SU1191941A1 - Device for recording information in matrix store - Google Patents

Abstract

A DEVICE FOR RECORDING INFORMATION TO THE MATRIX DRIVE, containing the first and second decoders, the outputs of which are the device outputs, AND, OR elements, and inverters, characterized in that, to simplify the device, it contains switches, a counter, a register, a driver, and the outputs The first and second groups of the first switch are connected to the inputs of the first and second decoders respectively, the inputs of the first group of the first switch are the address inputs of the first group of the device, the inputs of the second group. connected to the outputs of the register, and the inputs of the third group to the outputs of the second switch, the inputs of the group of which are connected to the inputs of the group of the third switch and the address inputs of the second group of the device, the outputs of the third switch connected to the outputs of the register, one control input of the counter connected to the output of the driver and the first control input of the register, and the other with the output of the first OR element, the output of the counter is connected to the first input of the AND element, the second input of which is connected to the output of the first inverter, and the output is connected to the first input of the second OR element, the output of which is connected to the control input of the first switch, and the second input is connected to the second control input of the register, the input of the first OR element and is the first control input of the device, the third control input of the register is connected and the second input of the first element OR is the second control input of the device, the input of the first inverter is connected to the third Q by the input of the first OR element, the first (L control input of the second switch, the first input of the third the OR element is the third control input of the device, the input of the imaging device is connected to the second input of the third OR element, the input of the second inverter and is the fourth control input of the device, the output of the second inverter is connected to the second control input of the second switch, the output of the third OR element is connected with the control input of the third switch, and the third input of the third element OR co is the fifth control input 4: devices, the information input of the register is the address input of the device.

Description

The invention relates to memory devices and can be used to create large semiconductor integrated memory circuits (LSI).

The spruce of the invention is the simplification of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2-4 are functional diagrams of the device in the cases of elontact, push-pull, and multi-stroke input of the address; in fig. 5 is an example of a functional circuit of an LSI memory with a tunable organization.

The device for recording information in the matrix storage device contains the first 1 and second 2 decoders, the outputs 3 of which are the outputs of the device, first 4, second 5, third 6 switches, register 7, counter 8, driver 9, element 10, first 11, second 12 and the third 13 elements OR, the first 14 and the second

15 inverters. In addition, the following notation is introduced: 16, 17, and 18 — address AO, dictionary Ac and bit Ar inputs of the device; 19 and 20 - the first THi and second TI2 clock inputs of the device; 21, 22 and 23 - the first PP, the second VTA and the third VC control inputs of the device.

BIS memory 24 (FIG. 5) contains a device 1 for recording information in a matrix storage unit, memory unit 25, unit 26 for data input / output. In addition, in FIG. 5 are designated: BP - input of the choice of LIS bit size; IN / OUT. - I / O for multi-bit I / O; BX.Q, OU.O — input and output for one-bit I / O.

The device operates as follows.

Depending on the required tact of entering the address, the signals presented in the table should be sent to the device inputs.

Single A, AP, VKAKO, VTA, PP,

Push-pull A,., VK, TI2 AO, PP, TI1 A ,,, BTA

Multicast AO, VK, THi TI2

The signal "O, entering the input of the VC device, initiates the address input mode. At the same time, at the output of the imaging unit 9, the setup signal is generated in the initial state of the register 7 and the counter 8.

With single-input input, the address of the discharge goes to the group of second inputs of switch 4 from the inputs of the device Ap (Fig. 2), and the address of the word from the inputs of the device Ac through switch 5 to the group of first inputs of switch 4. From the outputs of switch 4, the address is supplied through the dictionary I and bit 2 decoders to the inputs of the memory block 25.

The device provides maximum performance when entering addresses.

When pushing the address (Fig. 3), the address of the word is first entered into one of the bits of register 7 from the group of first outputs of switch 6. In the second cycle, using the clock signal "O at the input of the device TI2, the address of the word is recorded in the other register bits 7 sec. groups of second outputs of switch 6. From the outputs of register 7, the full address goes to groups of third and fourth inputs of switch 4.

TI |, TI2

AO, Au9, BTA, RR

The device provides a reduction

the number of inputs for entering the address twice at a sufficiently high speed.

In the case of a multi-cycle address entry (Fig. 4), the complete address is sequentially recorded in 2g steps in register 7 through the input of the AO device. Address address synchronization is performed using clock signals at the input of the device TI |. At the same time, the number of clock pulses is counted by the counter 8. When this number is 2 tons, the signal "1." Is generated at the output 5 of the element OR 12. In this case, the supply of address and clock signals should stop. The address from the outputs of register 7 is supplied to the inputs of switch 4.

The device provides a reduction in the number of inputs several times.

The proposed device for entering addresses is most preferable to be used in an LSI memory with a tunable organization, which allows using 5 different modifications of the device.

The LSI memory with a tunable organization functions, for example, as follows (FIG. 5).

In the well-known LSI memory, it is possible to implement single-bit or multi-bit I / O data. For a one-bit organization, the control input of the VR BIS memory is connected, for example, with the input "Power supply (signal" 1), and for multi-bit memory, with the input "Earth (signal" O).

The introduction of the proposed device for entering an address into a known LSI memory allows the following LSI modifications to be implemented: one-bit with a single-entry address entry; a one-bit address with multi-entry addressing or a similar-address address, but multi-bit modifications.

To rebuild the organization of the LSI memory, it is necessary to send signals to its inputs in accordance with the table for the device and the necessary signal to the input of the BP.

Technological modifications of the LSI memory can be performed in several ways. For example, at the production stage of the device, the connection of the control inputs of the LSI memory to the inputs of the Power Supply and the Earth is made by applying the necessary metallized compounds, at the assembly stage of the LSI - by connecting the necessary contact pads to the inputs of the Power Supply and Earth,

It is advisable to use a modification of an LSI memory with multi-bit data input-output and single-input address input in a small volume of memory and with increased speed, for example, in a high-performance memory device. The use of single-bit LSI memory with push-pull address entry allows you to create, for example,

 high-capacity operational memory. And a one-bit modification with a multi-entry address or a modification with a multi-entry address, or a modification with a minimum number of inputs can find

Q application when creating an external storage device. Other modifications of the LSI memory should be used in memory with intermediate characteristics.

Pu3. 2

pue. four

FIG. J

/ IP TI, 7Hz

8) 0 -4 3er / x.o

Pue. five

Claims (1)

A DEVICE FOR RECORDING INFORMATION IN A MATRIX DRIVE, containing the first and second decoders, the outputs of which are the outputs of the device, AND, OR, inverters, characterized in that, in order to simplify the device, it contains switches, a counter, a register, a shaper, and the outputs of the first and the second groups of the first switch are connected to the inputs of the first and second decoders, respectively, the inputs of the first group of the first switch are address inputs of the first group of the device, the inputs of the second group are connected to the outputs the register, and the inputs of the third group - with the outputs of the second switch, the inputs of the group of which are connected to the inputs of the group of the third switch and are the address inputs of the second group of the device, the outputs of the third switch are connected to the outputs of the register group, one control input of the counter is connected to the output of the shaper and the first the control input of the register, and the other with the output of the first OR element, the output of the counter is connected to the first input of the AND element, the second input of which is connected to the output of the first inverter, and the output is connected to the first the course of the second OR element, the output of which is connected to the control input of the first switch, and the second input is connected to the second control input of the register, the input of the first OR element and is the first control input of the device, the third control input of the register is connected to the second input of the first OR element and is the second control the input of the device, the input of the first inverter is connected to the third to 5th input of the first OR element, the first control input of the second switch, f the first input of the third OR element and is the third with the input of the device Q, the input of the driver is connected to the second input of the third OR element, the S input of the second inverter is the fourth control input of the device, the output of the second inverter is connected to the second control input of the second switch, the output of the third OR is connected to the control input of the third switch, and the third input of the third element OR is the fifth control input of the device, the information input of the register is the address input of the device. f 1 191941