JPH0120512B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and includes:
More particularly, the present invention relates to an improvement in an apparatus configured to write sample data to a memory in accordance with a sample clock, and to make effective use of the memory area of the memory.

FIG. 1 is a block diagram showing an example of a conventional device, showing a part of a logic analyzer, in which DL ₁ is a latch circuit, SM ₁ is a memory,
PG ₁ is a pulse generation circuit, and AC ₁ is an address counter. Latch circuit DL ₁ is the sample clock
All bits of the sample data D are latched by the trailing edge of SCL, and the latched data D is sent to the memory _SM1 and other control systems. Pulse generation circuit PG ₁ is
Write pulse according to sample clock SCL
A write pulse that generates WR.
WR is sent to memory _SM1 and address counter _AC1 . The memory SM ₁ has a data width corresponding to the number of bits of the sample data D and a data width corresponding to the number of bits of the sample data D.
The memory area is sufficient for the number of samples. The address counter AC ₁ sends the memory address A to the memory SM ₁ , and updates the memory address A every time one write of the sample data D is completed.

FIG. 2 is a time chart showing the operation of FIG. 1, where a is the sample clock.
SCL, b is sample data D, c is write pulse WR, and d is memory address A. Sample data D is latched in latch circuit DL ₁ at time t ₁ corresponding to the trailing edge of sample clock SCL, and latched sample data D is transferred to memory address A at time t ₂ corresponding to the trailing edge of write pulse WR. It is therefore written to memory SM ₁ .

By the way, in such a device, the memory SM ₁ must have a data width corresponding to the total number of bits of the sample data D (for example, in the case of 40 bits, ten 4-bit memories are connected in parallel). However, the number of data samples is memory SM ₁
If the number of addresses is small compared to the number of addresses (for example, the number of data samples is 256 maximum, but the number of addresses is
1000), the memory usage efficiency becomes a considerably low value.

The present invention focuses on such points and improves memory usage efficiency by writing sample data into memory in a time-sharing manner.

A detailed explanation will be given below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention, and shows an example applied to a logic analyzer, in which DL ₂ and DL ₃ are latch circuits,
MPX is a multiplexer, SM ₂ is a memory, PG ₂ is a pulse generation circuit, and AC ₂ is an address counter.

Latch circuits DL ₂ and DL ₃ are sample clocks.
All bits of the sample data Da and Db inputted by the trailing edge of SCL are latched, and the latched data Da and Db are sent to the multiplexer MPX and other control systems. Pulse generator circuit PG ₂ generates write pulse WR according to sample clock SCL.
In this embodiment, two consecutive pulses are generated. This write pulse WR is used for memory SM ₂ and address counter
Sent to AC ₂ . The multiplexer MPX outputs the data Da, latched in each latch circuit DL ₂ , DL ₃ .
Db is selected for each latch circuit and sent to the memory _SM2 as output data Dc. memory
SM ₂ has a data width corresponding to at least the maximum number of bits of the data Dc sent from the multiplexer MPX, and uses a memory area having at least twice the number of data samples as an address. For example, sample data Da,
If each Db has a 20-bit configuration, five 4-bit memories connected in parallel may be used. The address counter AC ₂ sends the memory address A to the memory SM ₂ and also sends the memory address A to the multiplexer.
It sends a switching signal Sc to the MPX. In this embodiment, the LSB of the address counter _AC2 is used as the switching signal Sc, and is also used as the switching signal of the memory address A.

FIG. 4 is a time chart showing the operation of FIG. 3, where a is the sample clock.
SCL, b is sample data Da, Db, c is write pulse WR, and d is memory address A. The sample data Da and Db are each set to the latch circuit at time _t1 corresponding to the trailing edge of the sample clock SCL.
The latched sample data Da and Db are latched in DL ₂ and DL ₃ , and sent to the memory SM ₂ as sample data Dc in units of latch circuits via the multiplexer MPX. The sample data Dc sent from the multi-sample MPX is a write pulse WR consisting of two consecutive pulses.
are written to the memory SM ₂ according to the memory address A at times t ₂ and t ₃ corresponding to the trailing edge of .

According to such a configuration, the memory area usage efficiency can be doubled compared to the conventional configuration.
The number of memory can be reduced.

In the above embodiment, an example was explained in which two series of data each consisting of 20 bits are handled, but the present invention is not limited to this, and it is also possible to handle a plurality of m series of data with different bit configurations. In this case, m latch circuits are provided, a memory having a data width of at least n bits corresponding to the maximum bit configuration and a memory area corresponding to at least m times the number of data samples is used, and a multiplexer is used to connect the latch circuits. It is sufficient to send the data selectively latched in units to the memory.
According to such a configuration, the memory usage efficiency can be increased by m times compared to the conventional example.

As described above, according to the present invention, a memory device with high memory utilization efficiency can be realized, and the practical effect is great as a memory device for various electronic devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional device.
FIG. 2 is a time chart showing the operation of FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a time chart showing the operation of FIG. 3. DL...Latch circuit, MPX...Multiplexer, PG...Pulse generation circuit, SM...Memory,
AC...Address counter.

Claims (1)

[Claims] 1 A plurality of m latch circuits that simultaneously latch a plurality of m sequences of data each consisting of a maximum of n bits according to a common sample clock, and a latch circuit that has a data width of at least n bits and is at least m times the number of data samples. A memory having a memory area corresponding to an address, a multiplexer that selectively sends the data latched in each latch circuit to the memory in latch circuit units, and a plurality of m continuous write pulses generated every sample clock. A memory device comprising a pulse generation circuit and an address counter that counts write pulses and generates an address signal, and writes a plurality of m sequences of data to a memory in a time-division manner.