JP2001282186A - Led display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a LED display device for displaying plural lines with a simple and low cost circuit configuration. SOLUTION: A screen display control part 104 and a line control counter 110 read all the display data by repeating such operation as they sequentially read a 1st raster portion of each display line stored in VRAM 106 and then sequentially read a 2nd raster portion of each display line. A parallel-serial conversion part 108 serializes these read display data and sends them to the LED panel. A timing generation part 109 generates a clock for transmitting the data from the parallel-serial conversion part 108 and signals for indicating delimitation of each raster and that of one screen data, and sends them to the LED panel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LED display device, and more particularly to an LED display device capable of displaying a plurality of lines of character strings.

[0002]

2. Description of the Related Art In an LED display device, a character string is displayed on an LED panel line by line. FIG. 2 shows an outline of a basic configuration of a circuit for performing such display control, and displays one line. 2 includes a CPU 201 for controlling the entire display control, an oscillator 202 for generating an original clock for performing the display control, and a frequency divider 203 for dividing the output of the oscillator 202 to generate a transmission clock CLK of the display data. , Screen display control unit 20 for generating read address RA for reading display data from VRAM 206
4. A selector (MPX) 205 for selecting one of the write address WA from the CPU and the read address RA from the screen display control unit 204, stores display data from the CPU, and outputs the display data to the LED. V
A RAM 206, a bus driver 207 controlling a data bus gate when the CPU accesses the VRAM 206, a parallel-serial conversion unit 208 for converting parallel data read from the VRAM 206 into serial data, and A required LED control signal timing generator 209 is provided. The timing generation unit 209 includes the screen display control unit 2
04 with reference to the timing information TM from “LATC
H ”and the like are determined.

"RDATA" and "GDATA" output to the LED are red and green display data,
This is what has been written to the VRAM 206 from the PU 201. “LATCH” is a signal for holding and displaying data for one raster for a certain period, and “CLKLED” is a signal for serial data “R” from the parallel-serial conversion unit 208.
A clock signal for sending and latching "DATA" and "GDATA" to the LED.
T ″ is a signal that notifies the LED of data display for one row.

FIG. 3 is a time chart showing the display operation of the circuit shown in FIG. 2. Here, one character is composed of 16.times.16 dots and one line is composed of 20 characters. "RDAT" in FIG.
A "and" GDATA "are the first raster data R
O, GO, second raster data R1, G1, ... 16
The first raster data R15, G15,
For example, data RO which is “RDATA” of the first raster
Is composed of dot data CO of the first raster for 20 characters, dot data C1 of the second raster,..., And dot data C0 is obtained from dot rows DTO, DT1... DT15 (16 dots) synchronized with the clock CLK. Made up of The same applies to other raster data and dot data constituting them. The signal "LATCH" is
The data read from 206 is serialized by the parallel-to-serial conversion unit 208, and when the output of one raster is completed, the data is output from the timing generation unit 209 and the data of the raster is set in the LED. The data is displayed on the LED panel. The signal "RESET" notifies the LED of the end of one line of character data.

FIG. 4 shows a VRAM 20 in the circuit of FIG.
6 is a time chart showing a read / write operation of No. 6;
Even when the serial data output from the parallel-to-serial conversion unit 208 is continuous, the data is stored in the VRAM 20
Since the reading from 6 is a parallel operation, there is considerable room, for example, before reading the data RO and GO of the first raster and then reading the data R1 and G1 of the second raster. Therefore, usually, during this time, the selector 205 is controlled to change the write address WA from the CPU 201 to the VRA.
M206, and simultaneously turns on the bus driver 207 to write data from the CPU.

[0006]

The circuit shown in FIG.
This is for controlling display of lines. When displaying a plurality of rows, display control of each row is performed by using a part of the functions in a multiplexed configuration based on the circuit of FIG. FIG. 5 shows an example in which a character string of three lines is displayed. The multiplexed (triple) function is the screen display control unit 20
41 to 2043, selectors 2051 to 2053, VRA
M2061 to 2063, and parallel / serial conversion unit 2
At 081 to 2083, the individual circuits have the same functions as in FIG. However, this configuration has a problem that the number of parts increases due to the configuration of the device, the size of the substrate increases, and the cost increases.

An object of the present invention is to provide an LED display device capable of displaying a plurality of rows by a configuration in which the mounting area is not increased and the cost is reduced.

[0008]

SUMMARY OF THE INVENTION The present invention provides a CPU for generating display data to be displayed on a plurality of display rows of an LED panel.
And a VRAM for storing the display data generated by the CPU, and sequentially reading the first raster data of each row data of the display data stored in the VRAM, and then reading the second raster data of each row data. Display data read control means for controlling so as to repeatedly execute processing of sequentially reading until all display data of each row is read; and converting parallel data in VRAM address units read by this means into serial data to convert the read data into LED data. Parallel-to-serial conversion means for outputting to the panel, a clock for transmitting the serial data output from this means to the LED, and a signal indicating a break of each raster and a break of display data of one screen are generated and transmitted to the LED panel. LED table comprising: It discloses an apparatus.

Further, according to the present invention, when the display data read control means reads the display data of each address of the VRAM, the CPU writes the display data to the VRAM in an idle time until the display data of the next address is read. The present invention discloses an LED display device characterized by performing the following.

[0010]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing a configuration example of an LED display device according to the present invention, which has a function of displaying a character string of three lines. In the conventional circuit shown in FIG. 2, a VRAM, a parallel-serial conversion unit, etc., are prepared for three rows, and data for the character strings for three rows are simultaneously output to the LED in parallel, and these are timing-synchronized with a common clock “CLKLED”. Take LE
In the circuit of FIG. 1, the character string data of each line is sent out serially on a set of data lines on a line-by-line basis, and clocks for timing the transmission are separately generated for each line. The difference is that they are sent. Therefore, the capacity of the VRAM 106 is large because it stores three rows of data. However, since only one VRAM is required, the address selector 105 for accessing the VRAM 106 and the parallel-serial conversion unit 108 operate in a time-division manner. The circuit configuration is greatly simplified as compared with that of FIG. 5, and the cost can be reduced. Other CPU 101, oscillator 102, frequency divider 103, screen display control unit 104, bus driver 107
Etc. are substantially the same as those in FIG. 2 to FIG.

However, the LED display timing generator 109
Are the clocks “CLKLED1” to “CLKL” for each row.
Further, the line control counter 110 has a function of generating an ED3 ″. Based on information from the screen display control unit 104, the line control counter 110 determines which line of data is currently read, serialized, and converted. By generating an LM and supplying the generated LM to the LED display timing generation unit 109, the generation of each clock “CKLLED1” to “CLKLED3” is controlled, and the row information LM is transmitted to the selector 105. Screen display control unit 104
The address to which the row information LM is added is sent to the VRAM 106 as an upper address of the read address RA from the VRAM 106. Therefore, if the data of each row is stored in the VRAM at the address where the row information LM is the upper address and the position in the row is given by the read address RA, the screen display control unit 104 controls the control of one row in the same manner as in the related art. May be performed.

FIG. 6 is a time chart showing the display operation of the apparatus of FIG. 1 according to the present invention. First, data RO (0) and GO (0) of the first raster in the first row, and the data in the second row are displayed. The first raster data RO (1), GO (1), the first raster data RO (2), GO (2) in the third row are sent to the LED, and then the second raster data R1 in each row.
(0), G1 (0); R1 (1), G1 (1); R1
(2), G1 (2) is sent, and then the third, fourth,... Raster data is sent out sequentially. The position of the data in each row is timed by clocks “CLKLED1” to “CLKLED3”. Here, VR of each raster data
The reading from the AM 106 and its conversion to serial data are the same as in the prior art (however, the address at the time of VRAM reading is also controlled by the row control counter output as described above). The signal "LATCH" is output at the time when the transmission of one raster of each row is completed, and the data set / display on the LED is performed. The signal "RESET" is output when the display of each row is completed.

As shown in FIG. 6, when data of three rows is read out from the VRAM in a time-sharing manner and output, it takes about three times as long to send one line of data as in the prior art. For this reason, the VRA for each line as described in FIG.
The extra time between data reading from M becomes smaller than before, and there is a possibility that data writing from CPU may be hindered. Therefore, in the present invention, a write access from the CPU is performed during a vacant time between read accesses to each address of the VRAM. FIG. 7 shows this VRAM
This is a time chart showing an access operation, in which a data read for one character in an arbitrary raster and a CP executed during the data read are performed.
The write operation from U is shown. One character is now 16
Since it is a dot, one character period is between 16 pulses of the clock CLK. Assuming that data of 8 bits (1 byte) is read for one read address RA in one clock, red RDATA may be read twice and green GDATA may be read twice in this one character period. . In FIG. 7, reading of RDATA is performed at address r.
0, r1 (fourth and twelfth clocks), and GDAT
It is assumed that reading of A is performed at addresses g0 and g1 (eighth and sixteenth clocks). Then, the necessary read operation can be performed in a total of four clock periods.
The clock period is allocated to the write operation from the CPU. As described above, by controlling the selector 105 to switch the write address WA from the CPU 101 and the read address RA from the screen display control unit 104 in a short cycle, time required for a write operation from the CPU is secured. be able to.

[0014]

According to the present invention, it is possible to realize an LED display device for displaying a plurality of rows with a smaller number of parts and costs than conventional ones.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an LED display device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a conventional LED display device.

FIG. 3 is a time chart showing a display operation in the device of FIG. 2;

FIG. 4 is a time chart illustrating a VRAM operation in the device of FIG. 2;

FIG. 5 is a block diagram illustrating a configuration example of a conventional LED display device that performs multi-line display.

FIG. 6 is a time chart showing a display operation in the device of FIG. 1;

FIG. 7 is a time chart illustrating a VRAM operation in the device of FIG. 1;

[Explanation of symbols]

 101 CPU 104 Screen display control unit 105 Selector 106 VRAM 107 Bus driver 108 Parallel-serial conversion unit 109 LED display timing generation unit 110 Row control counter

Claims (2)

[Claims] 1. A CPU for generating display data to be displayed on a plurality of display rows of an LED panel, a VRAM for storing display data generated by the CPU, and the VRAM
The first raster data of each row data of the display data stored in the row data is sequentially read out, and then the second raster data of each row data is read out.
Display data read control means for controlling the sequential reading of raster data until all display data of each row are read, and converting the parallel data in VRAM address units read by this means into serial data A serial-to-serial conversion means for outputting the serial data output from the means to the LED panel, a clock for transmitting the serial data output to the LED to the LED, and a signal indicating a break of each raster and a break of display data of one screen. An LED display device comprising: timing generation means for transmitting the signal to a panel. 2. When the display data read control means reads the display data of each address of the VRAM, the CPU writes the display data to the VRAM during an idle time until the display data of the next address is read. The LED display device according to claim 1, wherein the LED display device is configured as described above.