JPH02311895A - Bit map display control circuit - Google Patents

Abstract

PURPOSE:To shorten the width of display data between a bit-map memory and parallel-serial converting circuits by adjusting a time difference due to time division so that display data of respective planes outputted as serial signals from the respective parallel-serial converting circuits to a display output converting circuit at the same time. CONSTITUTION:Display data by respective planes A - D are read on a time- division basis out of the bit map memory 10 stored with display data of the plural planes and loaded in the parallel-serial converting circuits 11a - 11d corresponding to the respective planes, and the time difference due to the time division among the display data of the respective planes outputted as the serial signals from the respective parallel-serial converting circuits 11a - 11d is adjusted to make it ready to output the display data of the respective planes. Therefore, the display data of the planes stored on the bit map memory 10 can be transferred on a time-division basis, word by word, to the parallel-serial converting circuits 11. Consequently, the data transmission bus 12 between the bit map memory 10 and parallel-serial converting circuits 11 need to have only one-word data width.

Description

[Detailed Description of the Invention] [Objective of the Invention 1 (Field of Industrial Application) This invention relates to a bit map display control that controls and outputs display data of multiple planes read from a bit map memory to a display device of a combiator. Regarding circuits.

(Prior Art) FIG. 3 shows a conventional bit map display control circuit that controls the conversion of display data from a bit map memory into a display output of a display device.

The map memory 30 stores display data for a plurality of planes, and under the control of the display controller 31, the display data for each plane is transferred from the bit map memory 30 to parallel-serial conversion corresponding to each plane. They are simultaneously sent to circuit 32 (A-N). The display data converted into a serial signal by the parallel-serial conversion circuit 32 (A-N) is sent to the display output conversion circuit 3.
3, the signal is converted into a display output signal and sent to a display device (not shown) such as a CRT.

(Problems to be Solved by the Invention) In the above-described conventional bit map display control circuit, the display data of each plane is transferred from the bit map memory 30 simultaneously every - word display period, and -
The word is the data width by which the display data of each plane is transferred to each parallel-serial conversion circuit 32 (AN). Therefore, the data width of the bit map memory 30 and the parallel-serial conversion circuit 32 (A-N) is
If there are N planes, the width is N words.

That is, if the - word display period is, for example, 16 dots, the data width is Nx16 bits, and the number of signal lines 34 for transmitting display data is Nx16, which is very large.

Therefore, in the conventional bit map display control circuit, the data width between the bit map memory 30 and the parallel-to-serial converter circuit 32 (A-N) is large, making it difficult to design the circuit board. - Since the data width of the IC RAM chip used in the memory 30 is limited, there are various drawbacks such as the need for a large number of IC RAM chips.

The present invention was invented to eliminate these drawbacks, and provides a display control circuit for display data that reduces the data width of display data between a bit map memory and a parallel-to-serial conversion circuit. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) The present invention reads display data for each plane in a time-sharing manner from a bit map memory that stores display data for multiple planes to correspond to each plane. The display data of each plane is loaded into a parallel-to-serial conversion circuit, and the time difference due to time division of the display data of each plane outputted as a serial signal from each parallel-to-serial conversion circuit is adjusted by a, thereby aligning the output of display data of each plane. shall be.

(Function) The display data of multiple planes stored in the bit map memory can be transferred to the parallel-to-serial conversion circuit word by word on a time-division basis for each plane. The data transmission path between the parallel-to-serial converter and the parallel-to-serial converter circuit is sufficient to have a data width of -word (Embodiment) Next, an embodiment of the present invention shown in the drawings will be described in detail. Fig. 1 is a block diagram showing the configuration, and Fig. 2 is a timing chart of each signal. In one illustrated example, there are a plurality of planes (A-D), for example, four planes, and the display period of one word is 16 dots. The bit map display control circuit for the case shown in FIG. 10 is a bit map memory that stores display data of four planes (A-D); 1
1 (i=d) are four parallel-to-serial conversion circuits that convert display data of each plane (A-D) from this bit map memory 10 into serial signals, respectively.

The data width of the display data from the bit map memory 10 is 16 bits corresponding to one word.
Data transmission path 12 for display data between 1(a-d)
is composed of 16 signal lines.

This data transmission bus 12 has four planes (A to D).
display data and four parallel-serial conversion circuits 11
(a-d) are shared.

Of each parallel-serial conversion circuit 11 (a-d), a 12-bit shift register 13a is on the output side of the parallel-serial conversion circuit 1fa, and an 8-bit shift register 13a is on the output side of the parallel-serial conversion circuit 11b.
3b, a 4-bit shift register 13c is provided on the output side of the parallel-serial conversion circuit 11c,
The serial signals of the display data of each plane (A to C) are shifted to align the output timing.

14 is a display controller. Display controller 1
4 represents each plane (A
-D) by the address signal sent from the address specification path 15, and read transfer timing signals 16 (a-d) that transfer display data for each plane (A-D) to the data transmission path 12 in a time-sharing manner. Lead signal line 1
7 to bit map memory 10.

18 converts serial signals of display data from each parallel-serial conversion circuit 11 (a to d) into a display output signal of a display device (not shown) according to a control signal of the display controller 14 sent from a control signal line 19. This is a display output conversion circuit that converts and outputs.

The display controller 14 has a built-in clock signal 20 generation source, and a parallel-serial conversion circuit 11 (a
-d), the shift register 13 (a-e), the display output conversion circuit 18, etc. operate according to the timing of the clock signal 20 sent from the clock signal line 21 by the display controller 14.

Furthermore, when the display controller 14 and each parallel-serial conversion circuit 11 (a-d) are opened, a load timing signal 22 (a- d) Load timing signal used to transmit @23
(a-d) are provided respectively.

tf'J Display data read transfer timing signal 16 (a-d) from bit map memory 10, clock signal 20, display data load timing signal 22
Each timing of (a-d) is shown in the timing chart of tJS2 diagram.

Each shift width of each of the above shift registers 13 (a-e) is:
Each time difference between the display data of plane D read last from the bit map memory 10 by the display controller 14 and the display data of other planes A, B, and C read from the bit map memory 10; Each is set to the corresponding bit width.

Specifically, the shift register 13a will be explained based on the clock signal 20 with reference to FIG. Since the time difference between the timing signal 16d and the load timing signal 22d is 12 clocks, the shift register 13m has a shift width of 12 bits.

Similarly, regarding planes B and C, plane B.

C read transfer timing signals 16b, 16c* or load timing signals 22b, 22e, and read transfer timing signal 16d or load timing signal 22.
Since the time difference is 820 clocks and 4 clocks, the shift register 13b has a shift width of 8 bits, and the shift register 1.30 has a shift width of 4 bits.

As will be described later in connection with the claims, the display controller 14 specifies the address of each plane (A-D) and displays display data for each plane (A-D) in bits in a time-sharing manner.・Works as display control means for reading from the map memory 10 and transmitting it to the parallel-to-serial conversion circuits 11 (a-d) corresponding to each plane (A-D), and each shift register 13 (a-c) The time difference due to the time division is adjusted so that the display data of each plane (A-D) output as a serial signal from each parallel-serial conversion circuit 11 (a-d) is simultaneously input to the display output conversion circuit 18. It works as a time difference adjustment means.

Next, the operation of the present invention will be explained with reference to the drawings.

Within one word display period of 16 bits, a high level read transfer timing signal 16 (a-d) with a width of 4 clocks is sent from the display controller 14 to the bit map memory 10.
is time-divided into four times and sent through the read signal line 17. At this time, each read transfer timing signal 16 (&~d
), an address signal designating the address of each plane (A-D) is sent to the bit map memory 10 by an addressing bus 15. That is, when the first read transfer timing signal 16a is output during the - word display period, an address signal specifying plane A is output from the display controller 14 to the address designation bus 15, and the second read transfer is performed. When the timing signal 16b is output, the address signal specifying plane B is sent to the address specification bus 15.
is output from the display controller 14, and similarly from the third
When the read transfer timing signal 16c is issued for the fourth time, an address signal for plane C is output, and when the read transfer timing signal 16d is issued for the fourth time, an address signal specifying plane D is output.

When the read transfer timing signal 16 (a-d) is input to the bit map memory 10, the addressing path 15 is connected to the data transfer path 12 while the read transfer timing signal 16 (a-d) is at a high level. The display data of the plane (A-D) specified by is output.

Therefore, data transmission path 12 includes clock signal 20.
The display data of each plane (A-D) is outputted every 4 clock widths, and this is repeated every -word display period.

Furthermore, the display controller 1
4, a high-level load timing signal 22 (a-d) having a width of 170 clocks of the clock signal 20 is outputted to each load timing signal line 23 (a-d) at an interval of 3 clocks of the clock signal 20. Ru.

With each load timing signal @23 (a-d),
The load timing signal 22a is sent to the parallel-serial conversion circuit 11a, the load timing signal 22b is sent to the parallel-serial conversion circuit 11b, and the load timing signal 22a is sent to the parallel-serial conversion circuit 11a.
2c is a parallel-serial converter circuit 11c, and a load timing signal 22d is a parallel-serial converter circuit li.
d. Parallel-serial conversion circuit 11
When the load timing signal 22 (a-d) is input to (a-d), the display data output to the data transmission path 12 at this time is transferred to the parallel-serial conversion circuit 11.
(a-d). Specifically, when the load timing signal 22 (a=d) is at a high level and the clock signal 20 rises, the display data on the data transmission path 12 is loaded into the parallel-serial conversion circuit 11 (a-d).

The display data loaded into the parallel-to-serial conversion circuits 11 (a-d) is converted into a serial signal according to the timing of the clock signal 20, and the parallel-to-serial conversion circuits 11 (a, b, e) are converted to a serial signal by a shift register 13. (Turtle, b%C) is shifted and output to the display output conversion circuit 18.

- The bit map is displayed for the fourth time in the word display period.
The display data of plane D read from the memory 10 is loaded into the parallel-to-serial conversion circuit 11d, and the display output conversion circuit 18 is loaded at the rising edge of the first clock signal of the next word display period indicated by the symbol to in FIG. Output starts at .

At this time, as described later, other planes (A, B
, C) are also output in synchronization from the shift registers 13 (a-c) provided at the subsequent stages of the respective parallel-to-serial conversion circuits 11 (a, b, c).

Next, the data is read from the bit map memory 10 by time division, and each parallel-to-serial conversion circuit 11 (
The operation in which the display data of each plane (A to D) loaded in a to d) is simultaneously input to the display output conversion circuit 18 will be described.

The display data of plane A and plane D is transferred to the parallel-serial converter circuit 11a and the parallel-serial converter circuit li.
The difference in timing loaded into d is 12 clocks of clock signal 20. However, since a 12-bit shift register 13a corresponding to this difference is provided at the subsequent stage of the parallel-serial converter circuit 11a, the display data converted to a serial signal is transferred within the N7 trender 13a according to the clock signal 20. Shift each bit 12 times.

The display data of plane A is output from the shift register 131L at the rising edge of the first clock signal 20 in the next one-word display period indicated by the symbol to, and the output timing of the display data of plane D is output from the parallel-serial conversion circuit lid. Synchronize with.

Similarly, regarding the display data of the planes (B, C), the parallel-to-serial converter circuit 11b and the parallel-to-serial converter circuit lie have 8 bits and 4 bits, respectively, corresponding to the difference from the load timing of the display data of the plane D. shift register 13b and shift register 13cfJ
' Since the display data of plane B and plane C are shifted by 8 bits and 4 bits, respectively, the output timing is synchronized with the display data of plane A output from the parallel-serial conversion circuit lid. Become.

Next, the display device connected to the focus map display control circuit of the present invention and the operation of the present invention will be explained.

In the bit map display method, for example, C shown in FIG.
Some RT display screens 24 are composed of 500 scanning lines with 720 dots per scanning line.
To explain an example of this case, in the embodiment of the present invention,
Since the display period of one word is 16 dots, the bit
Words are sequentially read from the map memory 10 one by one, and one scanning line is displayed using 45 words of display data.

The display controller 14 controls the display output conversion circuit 18, and has a display period TH of 45 words for displaying one scanning line.
(e.g. 33 μg), bit map memory 10
outputs the display data from the display output conversion circuit 18, stops outputting the display data during the non-display period TL when the scanning line is folded back, and opens the non-display period TL (for example, 9 μs).
For example, the display controller 14 outputs a display control signal 25 to the display output conversion circuit 18, which causes the display output conversion circuit 18 to output a signal that does not illuminate dots on the screen. This display! The II control signal 25 is included in the control signal sent from the display controller 14 to the display output conversion circuit 18 via the control signal line 19, and as shown in FIG. Display period TL
is a low level.

For this reason, the bit map data from the display controller 14 is
The address signal outputted to the memory 10, the read transfer timing signal 16 outputted to the parallel-serial conversion circuit 11(a-d), the load timing signal 22, etc. are synchronized with the display control signal 25.

To explain more specifically, the display data of plane D is input from the parallel-serial conversion circuit 11cl to the display output conversion circuit 18 immediately at the start of scanning of the scanning line,
The display control signal 25 is controlled to rise to a high level when output from the conversion circuit 18.

The period from when the display data of plane A is loaded into the parallel-to-serial converter circuit 11a until the display data of plane D is input to the display output converter circuit 18 is that some signal is shifted by the clock signal 20. register 1
3(a-e) and the parallel-to-serial conversion circuit 11d are input to the display output conversion circuit 18, but since the display control signal 25 is at low level, the display output conversion circuit 18 outputs signals that do not cause a bright light. is output during the non-display period TL.

That is, since the display data of each plane (A-D) is read from the bit map memory 10 in a time-division manner, the display data of plane D is input to the display output conversion circuit 18 at the start of scanning of each scanning line. Although some unnecessary signals are input from the shift register (13a-c) and the parallel-to-serial conversion circuit 11cl to the display output conversion circuit 18 until the display is in the non-display period TL, they are not affected.

Since the display period of one word of 16 dots is shorter than this non-display period TL, the time difference between the display data of each plane (A-D) during the display period of one word is sufficiently absorbed and does not affect the operation.

For example, if the frequency of the clock signal 20 is 30Mz,
The period is 0.033...μS. The time difference between the display data of plane A and the display data of plane D is 12 clocks, so the time is 0.033...X12
=0.4 μs.

Since the non-display period TL is 9 μs, each plane (A
-D) The time difference between the display data is fully absorbed during the non-display period TL.

In short, in the above embodiment of the present invention, the four planes (A-D
) display data is 4 bits per word display period of 16 bits.
The parallel-to-serial converter circuit 11. is read in time-division manner and corresponds to each plane (A-D). (a-d)
and converted into a serial signal.

The time difference in display data between each plane (A to D) caused by being read from the bit map memory 10 in a time-division manner and loaded into each parallel-serial conversion circuit 11 (a to d) is determined by each shift register 13. (a-e), the input start timings of the display data of each plane (A to D) to the display output conversion circuit 18 coincide with each other.

In this way, in the above embodiment, the bit map memory 1
The data width of the display data sent from 0 to the parallel-serial conversion circuit 11 (a-d) is -16 of the word display period.
The data transmission bus 12 for display data is 16 bits.
Consists of main signal lines.

[Effect of the Invention 1 According to the present invention, the data width of display data between the bit-map memory and the parallel-to-serial conversion circuit is
This greatly reduces the cost, which simplifies circuit design, and has the extremely significant effect of requiring less RAM in the IC used for the bit map memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart 70, and FIG. 3 is an explanatory diagram for controlling display. FIG. 4 is a block diagram showing a conventional bit map display control circuit. 10...Bit map memory, 11...Parallel-serial conversion circuit, 12...Data transmission bus, 14...Display controller, 15...Address specification path, 16...Read transfer timing Signal, 22...Load timing signal.

Claims (1)

[Claims] Display data for each plane is read from a bit map memory that stores display data for multiple planes and converted into a serial signal by a parallel-serial conversion circuit, and each plane converted to a serial signal is In the bit map display control circuit that inputs the display data of the display into the display output conversion circuit and converts it into the display output signal of the display device, the address of each plane is specified and the display data of each plane is stored in the bit map memory in a time-sharing manner. Display control means read from the plane and transmit it to a parallel-to-serial conversion circuit corresponding to each plane, and display data for each plane output as a serial signal from each parallel-to-serial conversion circuit is simultaneously input to the display output conversion circuit. A bit map display control circuit comprising: time difference adjustment means for adjusting the time difference due to the time division.