SU1019444A1 - Function generator - Google Patents

Abstract

FUNCTIONAL GVREOSH A-. The EOVATVL, containing comparisons, a thru “counter, a register, a generator of impulses, three elements And a register of a Fuschad berth, the output of a comparison circuit is connected to the trigger input of the first and second alerovtov of the function register, which corresponds to the first and second outputs of the function register, different topics that, for the purpose of the {w} preconnected by intelligent hardware aAT () a, it combined the two memory blocks and the ratlf, Tfpspt & A output bits of the input register connect-11Ш with the nepei i input of the match circuit, the second the input of which is connected to the output of the first memory block, with the aid of the input {atvra connected to the output of the higher bit of the input register and through the second memory block to the installation input of the counter, rotated €)), the input of which is mowed and calculated | in the first and second alsods, the second entrances The players are connected to the output of the third 0Pent And, the first and second inputs of which are connected to the trigger and pulse generator outputs, the output of the reversible counter is connected to the input of the first memory block and the information input of the output register, the control input, KoTopoixt is connected to the output output . 4iii

Description

The invention relates to analog computing machines and may be used in analog and hybrid computing systems.

A functional converter is known that contains a series-connected analogue and a third converter (ADC), a storage device (memory), a digital-to-analog converter (DAC), the device input connected to the ADC input, the device output connected to the DAC output f 13,

The disadvantage of the device is the complexity, due to the large information capacity of the memory. ,

Closest to the invention is a device comprising an input register, a counter, triggers, AND elements, a control device, a comparison circuit, and a decoder CSj.

A disadvantage of the known device is the high hardware costs and complexity.

The chain of the invention is to control the converter to reduce hardware costs.

The goal is achieved by the fact that in the converter containing triggers, a counter, an input register, a pulse generator, a third element AND a function register, and the output of the comparison circuit coenvraeH with the first input / Grigger, the first inputs of the first and second elements And are connected respectively with the first and second outputs of the function register, it contains two memory blocks and an output register, and the output bits of the input register are connected to the first input of the comparison circuit, the second input of which is connected to the output of the first block, memory, second The second trigger input is connected to the high-end output of the input register and through the second memory block to the installation input of the trigger that has been executed; In particular, the summation and subtraction inputs of which are connected to the outputs of the first and second elements And the second inputs of which are connected to the spring of the third element And, the first and second inputs of which are connected to the outputs of the trigger and pulse generator, the output of the reversible counter connected to the input of the first memory block The information input input of the output register, the control input of which is connected to the output of the comparison circuit.

The drawing shows a block diagram 5 of the Converter.

Functional converter contains input register 1, blocks 2 and 3

AM, input 4 and output 5 transducer-j10 l, comparison circuit b, trigger 7, elements 8-10, reversible counter IjL, output / 1No register 12 pulse generator 13 and register: p function 14.

The device works as follows.

At input 4, variable X is supplied. At the output of register I, variable X appears and at its output

The high-order Q-signal, which transfers trigger 7 to a single state and allows entry of the contents of memory block 3 into reversing counter II. If a mono-stream of incremental output is reproduced, then block 15 contains the code of the smallest value of the function. At & g, the first output of the register of function 14 will be a signal of a logical unit that will open the element AND 9, and at the second output - a signal of a logical zero, which will close the elementary Y. If a monotonically decreasing function is played, then in block 3 there is a code the largest value of the function. This pulse generator 13 is connected to

the input of counter I. It is reversible counter 11 as it arrives, it reads the addresses of memory block 2, in which the codes of the approxmashmash nodes are stored. of the reproduced function, and if they coincide with the argument code, the comparison circuit will close the electronic tape E8 through trigger 7 and allow reading to register 12. This completes the calculation cycle.

The analysis carried out shows that the introduction of these nodes in I, by my grandfather, simplifies the device and increases the {{reliability of the functional transform).

On the considered principle, functional transducers can be constructed to reproduce any mono7 (FINAL functions.

Claims (1)

A FUNCTIONAL CONVERTER containing a comparison circuit, a trigger, a counter, an input register, a pulse generator, three AND elements and a function register, the output of the comparison circuit being connected to the first trigger input, the first inputs of the first and second AND elements connected to the first and second outputs of the function register characterized in that, in order to simplify the converter by reducing hardware costs, it contains two memory blocks and an output register, and the output of the bits of the input register is connected to the first input of the circuits comparison, the second input of which is connected to the output of the first memory block, the second input of the trigger is connected to the output of the highest bit of the input register and through the second memory block with the installation input of the counter, which is reversed, the inputs of the summed subtraction of which are connected respectively to the outputs of the first and second elements AND , the second inputs of the second are connected to the output of the third element And, the first and second inputs of which are connected to the outputs of the trigger and the pulse generator, the output of the reverse counter is connected to the input of the first the memory unit and the information input of the output register, the control input of which is connected to the output of the comparison circuit.