JPS55140954A - Block error correcting device - Google Patents

Block error correcting device

Info

Publication number
JPS55140954A
JPS55140954A JP4859279A JP4859279A JPS55140954A JP S55140954 A JPS55140954 A JP S55140954A JP 4859279 A JP4859279 A JP 4859279A JP 4859279 A JP4859279 A JP 4859279A JP S55140954 A JPS55140954 A JP S55140954A
Authority
JP
Japan
Prior art keywords
error
information
circuit
block
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4859279A
Other languages
Japanese (ja)
Other versions
JPS6040055B2 (en
Inventor
Eiji Fujiwara
Noboru Onishi
Katsuhiko Aoki
Shigeo Kaneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54048592A priority Critical patent/JPS6040055B2/en
Publication of JPS55140954A publication Critical patent/JPS55140954A/en
Publication of JPS6040055B2 publication Critical patent/JPS6040055B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To realize the correcting function for the single bit block error with a small bit number and the simple circuit constitution, by using together the 1-bit error correction, the single bit block error detection code and the block pointer each.
CONSTITUTION: Input information given from information source 1 is applied to syndrome producing circuit 3. Thus syndrome 4 is produced based on information 2 and then applied to syndrome decoding circuit 5 to be decoded. In such way, the error of information 2 is checked. And the error bit is pointed out in the case of the 1-bit error; while the error is pointed out among the erroneous blocks by using together block pointer 7 from block pointer generating circuit 6 in the case of the block error. Then error pointer 9 is applied to correcting circuit 10 for correction of information 2. At the same time, error detecting circuit 12 receives error detecting information from circuit 5, syndrome 4 and pointer 7 each, and then produces error type point-out signal 13 based on these information to then deliver signal 13.
COPYRIGHT: (C)1980,JPO&Japio
JP54048592A 1979-04-20 1979-04-20 Block error correction device Expired JPS6040055B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54048592A JPS6040055B2 (en) 1979-04-20 1979-04-20 Block error correction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54048592A JPS6040055B2 (en) 1979-04-20 1979-04-20 Block error correction device

Publications (2)

Publication Number Publication Date
JPS55140954A true JPS55140954A (en) 1980-11-04
JPS6040055B2 JPS6040055B2 (en) 1985-09-09

Family

ID=12807666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54048592A Expired JPS6040055B2 (en) 1979-04-20 1979-04-20 Block error correction device

Country Status (1)

Country Link
JP (1) JPS6040055B2 (en)

Also Published As

Publication number Publication date
JPS6040055B2 (en) 1985-09-09

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