JPS5546677A - Signal processor - Google Patents

Signal processor

Info

Publication number
JPS5546677A
JPS5546677A JP12081978A JP12081978A JPS5546677A JP S5546677 A JPS5546677 A JP S5546677A JP 12081978 A JP12081978 A JP 12081978A JP 12081978 A JP12081978 A JP 12081978A JP S5546677 A JPS5546677 A JP S5546677A
Authority
JP
Japan
Prior art keywords
data
codes
check
modulo
arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12081978A
Other languages
Japanese (ja)
Inventor
Ryoichi Wada
Mitsuharu Tsuchiya
Takanori Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12081978A priority Critical patent/JPS5546677A/en
Publication of JPS5546677A publication Critical patent/JPS5546677A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To obtain signal constitution of high correction performance by simple algorithm by adding several fixed check codes to data. CONSTITUTION:Through modulo-2 arithmetic of respective bits of data A to C, check code P is generated 101 and after an excessive code of fixed polarity is added to data A to C, check code Q is generated 102 from results of sequential shifts through modulo-2 arithmetic of each bit. In addition, data A to C and codes P and Q are provided 104 with check codes R1 to R5 for the detection of errors. Consequently, even if errors occur to two out of data A to C and codes P and Q, original data can be restored by remaining signals.
JP12081978A 1978-09-29 1978-09-29 Signal processor Pending JPS5546677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12081978A JPS5546677A (en) 1978-09-29 1978-09-29 Signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12081978A JPS5546677A (en) 1978-09-29 1978-09-29 Signal processor

Publications (1)

Publication Number Publication Date
JPS5546677A true JPS5546677A (en) 1980-04-01

Family

ID=14795740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12081978A Pending JPS5546677A (en) 1978-09-29 1978-09-29 Signal processor

Country Status (1)

Country Link
JP (1) JPS5546677A (en)

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