JPS5762646A - Error detection system - Google Patents

Error detection system

Info

Publication number
JPS5762646A
JPS5762646A JP55138063A JP13806380A JPS5762646A JP S5762646 A JPS5762646 A JP S5762646A JP 55138063 A JP55138063 A JP 55138063A JP 13806380 A JP13806380 A JP 13806380A JP S5762646 A JPS5762646 A JP S5762646A
Authority
JP
Japan
Prior art keywords
logical
parity
bit
binary data
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55138063A
Other languages
Japanese (ja)
Inventor
Toru Tejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55138063A priority Critical patent/JPS5762646A/en
Publication of JPS5762646A publication Critical patent/JPS5762646A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To detect the error of an output code where all constituent bits are changed to ''1'' or ''0'', by constituting a code obtained by adding an inversion discrimination bit to binary data with a parity bit added furthermore. CONSTITUTION:Binary data consisting of four data bits D0-D3 inputted to a storage device 11 is supplied from a register 2. This binary data is inputted to not only a parity generating circuit 13 but also a gate 5. The parity generating circuit 13 generaes a parity bit P2 on a basis of odd parity check. Meanwhile, the gate 5 sets an inversion discrimination bit CH to logical 1 when detecting that all data bits D0-D3 are logical ''1'' and sets the inversion discrimination bit CH to logical 0 when detecting that all data bits D0-D3 are logical ''0''.
JP55138063A 1980-10-02 1980-10-02 Error detection system Pending JPS5762646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55138063A JPS5762646A (en) 1980-10-02 1980-10-02 Error detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55138063A JPS5762646A (en) 1980-10-02 1980-10-02 Error detection system

Publications (1)

Publication Number Publication Date
JPS5762646A true JPS5762646A (en) 1982-04-15

Family

ID=15213105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55138063A Pending JPS5762646A (en) 1980-10-02 1980-10-02 Error detection system

Country Status (1)

Country Link
JP (1) JPS5762646A (en)

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