JPS56159814A - Error detecting method - Google Patents

Error detecting method

Info

Publication number
JPS56159814A
JPS56159814A JP6433880A JP6433880A JPS56159814A JP S56159814 A JPS56159814 A JP S56159814A JP 6433880 A JP6433880 A JP 6433880A JP 6433880 A JP6433880 A JP 6433880A JP S56159814 A JPS56159814 A JP S56159814A
Authority
JP
Japan
Prior art keywords
line
results
bit row
added
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6433880A
Other languages
Japanese (ja)
Inventor
Masanao Horie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6433880A priority Critical patent/JPS56159814A/en
Publication of JPS56159814A publication Critical patent/JPS56159814A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To easily perform error detection of high accuracy by subjecting the numbers of every bit row or line of inputted data to prescribed operations and comparing the results with the check codes of every bit row and line added to the input data. CONSTITUTION:The number of 1 or 0 is beforehand added to every bit row or line via a CPU5 to the binary data of the prescribed bit numbers inputted, and the results thereof are divided by >=3 integers, and the remainder of the results of said division are beforehand added as binary check codes to every bit row or line. When data are inputted through a card reader 2, the number of 1 or 0 for every bit row or line is added thereto via the CPU5, and the results thereof are divided by >=3 integers and the remainder of the results of said division and the check codes of every bit row or line added to the input data are compared, whereby the errors of the inputted data are detected. By such method, the error detection of high accuracy is accomplished easily without requiring intricate checkings.
JP6433880A 1980-05-15 1980-05-15 Error detecting method Pending JPS56159814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6433880A JPS56159814A (en) 1980-05-15 1980-05-15 Error detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6433880A JPS56159814A (en) 1980-05-15 1980-05-15 Error detecting method

Publications (1)

Publication Number Publication Date
JPS56159814A true JPS56159814A (en) 1981-12-09

Family

ID=13255349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6433880A Pending JPS56159814A (en) 1980-05-15 1980-05-15 Error detecting method

Country Status (1)

Country Link
JP (1) JPS56159814A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02210700A (en) * 1989-02-10 1990-08-22 Fujitsu Ltd Method for generating test data of mask rom integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02210700A (en) * 1989-02-10 1990-08-22 Fujitsu Ltd Method for generating test data of mask rom integrated circuit

Similar Documents

Publication Publication Date Title
JPS5323522A (en) Bar code reading method and its device
GB1498221A (en) Character recognition unit
GB1287238A (en) Error detection and correction apparatus
JPS56159814A (en) Error detecting method
JPS57188159A (en) Error check system
JPS5699573A (en) Kanji (chinese character) distinction system using katakana (square form of japanese syllabary)
JPS6488698A (en) Added character for self-checking erroneous reading of goods label
JPS5592054A (en) Unique word detection circuit
JPS52112243A (en) Error detection system for exclusive reading memory
JPS5743263A (en) Character processing equipment
ES470764A1 (en) Apparatus for reading and analysing bar code characters
JPS5335429A (en) Code reader
JPS6448151A (en) Data processor
SU896786A1 (en) Discrete information registering device
JPS5762646A (en) Error detection system
JPS5748169A (en) Optical character reader
JPS545416A (en) Data check system by crc
JPS56140754A (en) Processor
JPS6462736A (en) Error detecting circuit
SU135465A1 (en) The method of checking the correctness of assembling notebooks in the book block
SU754051A2 (en) Apparatus for rerecording of logging charts
SU381085A1 (en) METHOD FOR MONITORING THE OPERATIONAL CAPACITY OF THE READING
JPS57109088A (en) System for word retrieval
JPS5748131A (en) Data input device
JPS5430053A (en) Pointer inspecting device having erroe checking functions