KR930009533B1 - Video signal shuffling apparatus and method - Google Patents

Abstract

The apparatus for shuffling video signal in the digital VCR, comprises: a first controller for distinguishing first signal after reset, from output of an address counter, a delay means for delaying said first signal for predetermined time, an adder for adding sampling bit to said first signal, a second controller for comparing output of delay means with uppermost address, first switching means for reading or writing suffling signal to or from said second controller, first reset means for informing said address counter of output of the first switching means, a second reset means for resetting output of the second adder, and a second switches means for reading data of another memory during writing shuffling mode. Thus this invention can shuffle data almost without corelationship between data and corrective error sufficiently after randomizing burst error.

Description

Apparatus and method for shuffling video signals

1 is a conventional configuration diagram.

2 is a block diagram of the present invention.

3 is a sequence diagram of sample data in a shuffle memory according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Write address counter 2: Read address counter

3, 4: shuffle memory 5: first adder

5a: second adder 6: first controller

6a: second control unit 7: delay unit

8: first switching unit 8a: second switching unit

9: first reset section 9a: second reset section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for shuffling video signals. In particular, the present invention relates to a random error (Rander Error) of a burst signal of a video signal in a digital video cassette recorder (VCR).

In general, a recording device such as a digital VCR that digitally records an image signal records data at a high density. Therefore, the pitch between tracks is very small, and thus, a plurality of tracks are adhered to dust or scratches on the tape. In some cases, data may become impossible to reproduce.

In this case, if a random error occurs, the data is corrected by an error correcting code and the uncorrected data is appended with an error flag (Flag), and the correction is made by supplementing the data around the pixel with the error flag in the error correction step. However, if the defect area is large, even the data around the data used for correction will generate an error and error correction will be impossible.

In order to solve this problem, as a method of correcting a burst error in which an error occurs in a relatively wide range and simultaneously correcting a random error, a method of dividing a digital video signal into a plurality of channels and shuffling data in each channel is proposed. There is a bar.

Therefore, when data is shuffled and recorded, even when a burst error occurs during recording and reproduction, when reconstructed to the original screen, it becomes a random error and interpolates and corrects an error error corrected pixel.

In the conventional shuffling apparatus, as shown in FIG. 1, the write address signal S ₁₄ (S ₁₃ ) of the shuffling memory 10 (11) is the output signal S of the write address counter 12. ₁₂ ) is obtained by converting through a predetermined shuffle map (13), and the read address signal (S ₁₅ ) of the shuffling memory (10) is the output signal of the read address counter (14) It is configured to be given directly.

In addition, the read address signal S ₁₆ of the other shuffling memories 11 is configured such that the most significant bit output signal of the read address counter 14 is inverted via the most significant bit inversion circuit 15.

The digital image signal S ₁₀ (S ₁₁ ), which is divided into the A and B channels by the multiplexer at the front end and inputs to the two shuffling memories 10 and ₁₁ , is output through the shuffle map 13. According to the signal S ₁₄ (S ₁₃ ), two shuffling memories 10 and 11 are sequentially written.

The read address signal (S ₁₆₎ of the B channel is because the most significant bit is different from the read address signal (S ₁₅₎ for the shuffling memory 10 of A channel to the highest address in the shuffling memory 10 the address Address 0 When reading data sequentially, the shuffling memory 11 reads from the address corresponding to about 1/2 of the highest address to the highest address, and then returns to address 0 to read the remaining data.

This means that while the shuffling memory 10 reads data in the first half, the shuffling memory 11 reads data in the second half and the shuffling memory 10 reads data in the second half. It means to lead.

However, the conventional technology requires a complicated additional device to use a multiplexer and to divide data into a plurality of channels in order to use a plurality of channels, thereby complicating the overall device configuration.

In addition, since the correlation between write data is high, the ability to randomize it when a burst error occurs is insufficient.

The present invention is to eliminate the above-mentioned disadvantages, and shuffling of an image signal by using one channel and two frame memories capable of storing identically set frames as shuffling memory for effective shuffling The purpose is to provide a device.

In order to achieve the above object, the present invention includes two shuffling memories having the same frame storage capability, a write counter, and a read address counter, which are generated after inputting an output signal of the input address counter and resetting. A first control unit for dividing the first signal from other signals and outputting the first signal; a delay unit for inputting the first signal after the reset through the first control unit and delaying the predetermined signal corresponding to the sampling data section and then outputting the first signal; Inputs a signal other than the first signal and adds the output signal of the first adder, the delay unit and the first adder to add the same number of bits of sampling data, and compares it with the set highest address. A second control unit for outputting a control signal and the two shuffling memos according to the control signal of the second control unit Alternately writes sample data or switches to reset the address counter. When an output signal of a write address counter larger than the set maximum address is input through the first switch, the signal is reset and written. The first reset unit notifying the address counter, the second adder which adds one by one whenever there is a reset signal from the first reset unit, and applies it as the first signal to the write address counter, and the second addition equal to the set highest address. A second reset unit for resetting the write address counter when the negative output signal is inputted through the first switching unit; and a switching operation in reverse with the first switching unit so that one shuffling memory writes sample data. A second switching unit connects to the read address counter so that the stored data can be read. do.

This will be described below with reference to FIGS. 2 to 3, which are embodiments of the present disclosure.

2 is a block diagram of the present invention, which includes a write address counter 1, a read address counter 2, two shuffling memories 3 and 4, and first and second adders 5 and 5a. ), The first and the second control section 6 (6a), the delay section (7), the first and second switching section (8) (8a) and the first and second reset section (9) (9a) It is composed.

Here, the shuffling memory (3) (4) is the same frame memory that can store the frame when one frame is composed of 91 samples x 525 lines (Line), the data is written to one shuffling memory (3) And the storage data of the other shuffling 4 is read through the first and second switching units 8 and 8a.

In addition, as shown in FIG. 3, the data arrangement of the shuffle memory 3 (4) designates one index to one sample data, and the total address in the frame is from 0 to 477749 (91 x 5250-1). It consists of up to.

At the first operation, the first sample data is written to address 0 starting from the write address counter (1), the sampling interval is set to 91, and the second sampling data is written from address 91 to the third sampling data at address 182. The 5250 th sampling data is written to 477749 and the 5251 th sampling data is repeatedly written to the 92 to be alternately written to the shuffling memory 3 (4).

Therefore, the shuffle memories 3, 4 contain 0, 1, 2, 3... … 1st, 5251th, 105101th, 15751th in order of address… … Sample data for is written.

In one shuffle memory 3, when the write operation is completed up to the set maximum address, the write operation to the shuffle memory 3 is terminated by the second switching unit 8a, and the read operation is performed to the other shuffle memory 4. The first switching unit 8 is configured to write each sampling data of the next frame.

The operation of the present invention configured as described above will be described with reference to FIGS. 2 and 3.

First, the write address counter 1 is first generated from address 0 and sequentially increased after the first address is generated to repeatedly generate addresses up to 5250.

At this time, the first control unit 6 outputs the set sampling width after the reset signal 0 is input from the first reset unit 9 and the second reset unit 9a for the first time. The signal is output to the delay unit 7 so as to be delayed by a corresponding time, and other signals are output to the first adder 5.

The first adder 5 adds 91 to the input signal of the write address counter 1 and outputs it to the second controller 6a, which is smaller than the highest address 477749. In this case, the center terminal COM of the first switching unit 8 is connected to the terminal a and transferred to the shuffle memory 3 as a write address signal. If the value is larger than 477749, the center terminal of the first switching unit 8 is connected. (COM) is connected to the terminal (C) so that the value is reset in the first reset section (9). At this time, the second adder (5a) is added by one every time the reset is performed to the write address counter (1). To the first address after reset.

Therefore, the write address counter 1 outputs an address signal using the number received from the second adder 5a as the first address.

On the other hand, when the input value is equal to 477749, which is the highest address of one frame, the second control unit 6a connects the center terminal COM of the first switching unit 8 to the terminal b and accordingly resets the second reset unit. By the unit 9a, the write address count 1 outputs the address number starting from zero again, and the sample data starts to be written to the shuffle memory 4.

The output signal of the read address counter 2 is switched toward the shuffle memory 3 by the second switching unit 8a operating in reverse with the first switching unit 8 so that the contents of the shuffle memory 3 are sequentially stored. To lead.

At this time, the data order of the shuffle memory 3 to be read is 1, 5251, 10501, 15751, 1001... … Since 462000, 467250, 472500, and 477750 are in order, there is little correlation between the data, so that sufficient shuffling effect can be obtained.

Therefore, in the shuffle data 3, as shown in FIG. 3, the first sample data is written at 0, the second sample data is written at 91, the third sample data is written at 182, and the 10th sample data is written at 891. At the last address of the line, 909, the 52510th sampling data is written.

If you continue writing in this way, the last address of the frame, 477749, is written with the 477750th data, the last sampling data.

Thereafter, the write operation to the shuffle memory 3 is finished and the write operation to the other shuffle memory 4 is performed in the same manner, and at the same time, each sample data of the completed shuffle memory 3 is sequentially read by the read address counter 2. Leads.

As described above, according to the present invention, since the data can be shuffled so that there is little correlation between recorded data as a simpler device than the prior art, even when a burst error occurs, the burst error can be randomized and sufficient error correction can be performed. There is.

Claims (1)

2 having a write address counter and a read address counter for shuffle having the same frame storage capability, the output signal of the input address counter being input, and the first signal and other signals inputted after reset are output separately Delay unit 7 for inputting the first signal after the reset through the first control unit 6, the first control unit 6 and the delayed by a predetermined time corresponding to the sampling data width, and outputs the first control unit, and the first control unit Outputs of the first adder 5, the delay unit 7 and the first adder 5 for inputting signals other than the first signal through 6 and adding them to and outputting them by the width of the sampling data. The second control unit 6a for inputting a signal and comparing it with the set highest address number and outputting a control signal according to this, and the two shuffle memories alternately according to the control signal of the second control unit 6a. When the output signal of the first switching unit 8 and the write address counter larger than the set maximum address is inputted through the first switching unit 8, the sample data is written or switched to reset the address counter. A first reset unit 9 for resetting and informing the write address counter, and a first reset unit 9 for each reset signal from the first reset unit 9 and applying this as a first signal to the write address counter; The second adder 5a and the second reset unit 9a which resets the write address counter when the output signal of the second adder 5a equal to the set highest address is input through the first switch 8. And the reverse switching operation of the first switching unit 8 to connect to the read address counter so that the stored data of the other shuffle memory is read when one shuffle memory writes sample data. The shuffling unit of the video signal characterized in that it comprises a second switching unit (8a).