JPH0235666A - Video data recording or reproducing device - Google Patents

Abstract

PURPOSE:To deal with video data on a screen unit by making a read or write address and a write or read address have an offset to each other in accordance with the position information of screen changeover positions on a track. CONSTITUTION:A memory is provided to be inputted with video data to be recorded or reproduced video data. In addition, the device is provided with a position detecting means for detecting the screen changeover position of the video data on the track and an address control means for controlling an offset amt. of the write address and the read address in the memory corresponding to the screen changeover position detected by the position detecting means. By this method, data to be written in the memory or data to be read out of the memory can all be based upon the screen changeover position as a reference, so that the video data can be dealt with the screen unit.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is a video data recording or reproducing device suitable for a video data recording or reproducing device, particularly a video data recording or reproducing device in which the video data screen switching position is not uniform from track to track. Regarding equipment.

[Prior Art] FIG. 5 is a diagram showing a schematic configuration of a conventional general digital video tape recorder (DVTR).

Referring to FIG. 5, the operation during recording will first be explained. The input image signal is converted into digital data by an A/D converter 30, and redundant data is deleted by an encoder 31 using image correlation.

Next, an error correction code (ECC) is added by an ECC encoding circuit 32 as a measure against the occurrence of errors in the recording medium, and a digital code change 7A33 is performed to obtain a signal spectrum distribution suitable for magnetic recording and reproduction. Thereafter, the data is recorded on a magnetic tape 36 via a recording amplifier 34 and a recording head 35.

During playback, video data that has been recorded on the magnetic tape 36 is transferred to the playback head 37. Head amp 38, digital IWy
The signal at this stage, reproduced through the A unit 39, contains code errors related to the recording medium due to the dust, scratches, etc. mentioned above. Therefore, an ECC decoder 40 adds redundant information such as a synchronization signal to the primary signal that performs processing such as error correction, and a decoder 41 adds redundant information such as a synchronization signal.

Restore input information almost completely. Finally, the D/A converter 42 can restore an analog image signal similar to the input image information.

A large number of DVTRs having the above configuration have been developed in recent years, and most of these recording track patterns consist of a plurality of tracks forming one screen as shown in FIG.

For example, the video signal of the first field is recorded on tracks T and -T in FIG. 6, and the video signal of the second field is recorded on tracks T4-T6.

Further, it is common that the number of tracks formed for an l-field video signal is always an integer floor. This is due to its advantages when considering synchronized operation of the DVTR, one-shot continuous editing, variable speed playback, and the like.

[Problems to be Solved by the Invention] In recent years, technology for highly efficient encoding of image data has been rapidly progressing, mainly in the field of communication such as video conference systems and TVJ programs.

Furthermore, there is an increasing demand for long-duration recording for DVTRs.

Considering these points, it is possible to extend the recording time of DVTR even slightly by applying high-efficiency image encoding technology developed in the communications field, and this is something that will be actively implemented in the future. I think that the.

However, data further compressed by high-efficiency encoding,
When attempting to record at the highest possible density, the screen switching position of the video data recorded on the recording medium may not be constant on the recording track. In this case DVT
It becomes extremely difficult to input and output R video data in units of fields or frames. As mentioned above, this is synchronized operation of the DVTR and continuous shooting.

This leads to the difficulty of editing, etc.

However, if you make sure to record 1 field of video data, or 1 frame, on an integer number of tracks, you can compress until, for example, 1 field of video data can be recorded on 2.1 tracks. Even so, three tracks must be prepared for one field of video data, which hinders high-density recording.

The present invention was made against this background, and no matter where the screen switching position of the video data on the track is,
The object of the present invention is to provide a video data recording or reproducing device that can handle video data on a screen-by-screen basis.

[Means for Solving the Problems] To achieve this purpose, the video data recording or reproducing apparatus of the present invention records video data while forming a large number of tracks on a recording medium, or records video data from the tracks. A device for reproducing data, comprising: a memory into which video data or reproduced video data is input when recording is attempted; a position detecting means for detecting a screen switching position of the video data on the track; The present invention is configured to include address control means for controlling an offset amount between the write address and the read address of the memory in accordance with the detected screen switching position.

[Function] According to the above-described configuration, all data written to or read from the memory can be based on the screen switching position, and it has become possible to handle video data on a screen-by-screen basis. .

[Example] The present invention will be explained below using examples.

FIG. 1 is a diagram showing a schematic configuration of a digital data recorder as an embodiment of the present invention, FIG. 2 is a diagram showing the arrangement of cylinders and heads of the data recorder of this embodiment, and FIG.
Figures (A), ([1), and (C) are diagrams for explaining the recording format of this embodiment, and Figure 4 is a diagram showing the memory space of this embodiment.6 In Figure 1, 1 indicates recording. This is an input terminal for digital signals. 2 is a clock generator, and the clock generated by the clock generator 2 is.

The frequency is divided by a frequency divider 4 according to a frequency division ratio set in advance according to the amount of input data. The memory control circuit 5 uses the output clock of the clock generator 2 as a write clock to write the address.

A write-in enable signal is supplied to the RAM 7.

In this manner, data representing the input digital signal is written into the RAM 7. The drum control circuit 8 controls the drum rotation to synchronize with the (200/3) H2 rectangular wave signal output by the drum rotation detector 13 and the (200/3) Hz signal output from the frequency divider 4. do.

As shown in FIG. 2, the digital data recorder (DDR) of this embodiment has three adjacent heads 1 (a.

A magnetic tape 51 is wound over an angular range of 180° or more around a rotating drum 20 having three adjacent heads Hd, 11b, tic, and 11b, tic, which rotate with a phase difference of 180''. , a total of six heads record on the magnetic tape.

The heads Ila, fib, and Ilc have a 4I configuration that rotates by shifting each other a predetermined distance in the direction of the rotation axis, and the amount of shift is set according to the recording track pitch. The same applies to heads lid, lle, and Hf.

Assuming that the rotational speed of the head is 4000 rpm and the input data is image data with a vertical synchronization frequency of a60H,
The head will rotate 1079 times per 1 vertical synchronization period. Since the head is installed in the configuration shown in FIG. 2, the track pattern on the tape is such that data is recorded/reproduced on six tracks per revolution as shown in FIG. 3(C).

Figure 3 (A) shows the recording data format for one track in this embodiment, and the data string is constructed line by line from the upper left to the upper right in the figure, from the top to the bottom, and becomes the serial data for one track. . Is this simply illustrated in Figure 3 (B), where the direction from left to right of the data row of this one track matches the diagonal direction from the bottom right to the top left of each track in Figure 3 (C)? do.

Among these, assuming that the line indicated by a circle in Fig. 3 (A) is the vertical synchronization position of the input image data, the recorded data areas ■ and ■ shown in the figure correspond to the lines shown in Fig. 3 (B) and (C). But [corresponds to area ■, ■. In this embodiment, head 1
Since the vertical synchronization position is displayed every 0/9 rotation, the vertical synchronization position is not a constant position in the tape width direction, as shown in the positions ■ and ■ in Fig. 3 (C), and the position of It will be difficult to determine if it exists.

In FIG. 3(A), each line of data is divided horizontally into percentages on the tape, and each line is divided into subblocks (Sub B
lock) O, subblock (SubBlock) 1
A parity CI of an error correction code for correcting data errors on the tape is added as a parity CI. Furthermore, Sub Bl
Immediately before ock O, 1, a sync pattern 5 sync for block synchronization and ID data for block identification are added by the ID word adding circuit 10 in FIG. Furthermore, in order to further strengthen error correction, parity c2 of an error correction code for 4 lines is added to every 85 lines in the vertical direction. In order to identify the position of a block consisting of two sub-blocks, the ID data includes the block number representing the position of the vertical line where this block exists in the format shown in FIG. V data indicating whether the block is the first block from the vertical synchronization position of the data is also included. These block numbers and V data are the clock output from the clock generator 2 and the clock output from the PLL circuit 6.

Furthermore, it is formed by the memory control circuit 5 based on the vertical synchronization signal of the input image signal from the terminal 9.

Reading from the RAM 7 is performed by the memory control circuit 5 supplying a read enable signal and a read address to the RAM 7 using the clock output from the PLL circuit 6 as a read clock. The data read from the RAM 7 is distributed to three recording systems in units of data blocks, and error correction codes (FCC, EN) +5a, 15b are added to the above-mentioned C1 and C2 parities and 5sync.

+5c, and even a digital transformer (MOD) 16
a, 16b.

+5c, switch SWI, SW2. SW:R of l
It is supplied to each head via a terminal. As shown in the figure, heads Ha and Hd, heads Ilb and He, heads Hc and +If
are recording heads of the same system.

Next, the reproduction system will be explained. 3 played on each head
The reproduction signal of the system is transmitted through switches SWI and SW2.

Digital demodulator (DEM) via the P terminal of S'l13
21a, 21b, 21c, error correction decoders (ECC, DE) 22a, 22b, 22c
The data is subjected to error correction using 2 parity, etc., and is serially written into the RAM 7'.

FIG. 4 is a diagram showing the data storage area of this RAM 7'.
The horizontal direction corresponds to exactly one track's worth of data. Each of the data shown in Figure 4, ■~■, ■~0, is shown in Figure 3 (C
) But the same symbols are used.For example, let us consider the case where a synchronization digitizer is output to an external vertical synchronization signal during playback. At this time, the vertical synchronization position ■
can be known from the ID data indicating the block number in the reproduced signal and the V data included therein. That is, it is possible to recognize the line number in which the V data is included, that is, the horizontal offset amount shown in FIG. Therefore, the object can be achieved by sequentially reading out the read addresses of the RAM 7' shown in FIG. 4 with an offset amount (■) added thereto in synchronization with the external vertical synchronizing signal.

That is, the block number is extracted by the ID word extraction circuit 16 in FIG. 1, and the write address of the memory is controlled thereby. Further, the offset amount (1) is extracted by the memory control circuit 51 from the V data extracted at the same time.

An external vertical synchronizing signal for reading is inputted from the terminal 9, and by reading from the address of the offset amount (2) in synchronization with this, reproduced signal data synchronized with the external vertical synchronizing signal is outputted from the terminal 17.

In addition, in the above-mentioned embodiment, for the sake of simplicity, the RAM in the storage system is not used. In the embodiment described above, any external vertical synchronization is required. Since the video signal can be played back in sync with the signal, two D
Work such as synchronized operation of the VTR and editing can be easily performed.

Finally, a case in which the above embodiment is applied to continuous shooting will be briefly explained. Now, when the pause switch is pressed, data is stored in the RAM 7' as shown in FIG. At this time, it is assumed that the RAM is shared with the recording system RAM 7. The tape is once rewound by a predetermined length, and is then conveyed at a normal recording/reproducing speed while tracking is controlled.

Next, using information such as time code, each head writes the signals recorded at the timing to start tracing three tracks including the one shown in FIG. 3(C) from the RAM 7 until the timing for the RAM 7 to read them. Data is not read out, but data to be recorded is read out from the RAM 7 after the above timing at an address according to the block number. If you continue writing, you can perform continuous shooting.

In this way, when video data to be recorded is made to correspond to an arbitrary screen switching position on the track (this can be done by offsetting the write address).

[Effects of the Invention] As explained above, according to the present invention, no matter where the screen switching position on the track is, the read or write address and the write or read address can have an offset according to this position information. As a result, video data can be handled on a screen-by-screen basis, so even if video signals are recorded for as long as possible, there will be no disadvantages when processing various video signals.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the schematic configuration of a digital data recorder as an embodiment of the present invention, FIG. 2 is a diagram showing the arrangement of cylinders and heads of the digital data recorder of ER1 [7], FIG. 3 (A), (B) , ((:) is a diagram for explaining the recording format of the data recorder in Figure 1. Figure 4 is a diagram showing the data storage space of the RAM in Figure 1. Figure 5 is a diagram for explaining the recording format of the data recorder in Figure 1. Figure 5 is a diagram for explaining the recording format of the data recorder in Figure 1. Fig. 6 is a diagram showing the recording pattern on the tape by the DVTR of Fig. 5. In the figure, 1 is an image signal input terminal, 5.5' is a memory control circuit, 7, 7' is RAM, 9 is vertical synchronization signal input terminal, lO
is an ID word addition circuit, 16 is an ID word extraction circuit, 2
1 is a magnetic tape.

Claims (1)

[Claims] A device for recording video data or reproducing video data from the tracks while forming a large number of tracks on a recording medium, wherein the video data to be recorded or the video data to be reproduced is input. a memory for detecting a screen switching position of video data on the track; a position detecting means for detecting a screen switching position of video data on the track; and controlling an offset amount between a write address and a read address of the memory in accordance with the screen switching position detected by the position detecting means. A video data recording or reproducing device comprising address control means.