JPH03109886A - Video reproducing device - Google Patents

Abstract

PURPOSE:To improve picture quality at high speed search considerably by utilizing a video data of a block even when an error is caused in an identification data of the block when no dropout is detected. CONSTITUTION:The device is provided with an error detection means 22 detecting an error of a reproduced identification data, a dropout detection means 18 detecting the presence of dropout of a reproduction signal, and a logic means 32 presetting the identification data to a write address counter 26 when no error exists in the reproduced identification data, and advancing a prescribed number to the write address counter 26 when error exists in the identification data and the dropout detection means 18 detects no dropout. Thus, even when an identification data error of a synchronization block exists, so long as a video data is reproduced, the video data is stored in a memory means 30 and used for decoding the video image thereby improving the picture quality considerably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video playback device that plays back digitally recorded video signals.

[Prior Art] A digital video recording device that digitizes a video signal and records it on a recording medium includes, for example, a digital VTR. Digital VTRs use analog video signals (see Figure 4).
a)) is sampled and quantized and converted into, for example, 8-bit digital data DD (FIG. 4(b)).

Then, in order to prevent harmful effects caused by burst errors, the digital data DD is subjected to distributed processing such as shuffling, and further, as shown in FIG. 4(C), a predetermined number of digital data DD is Create a block, add a block synchronization signal 5YNC to the beginning, and deshuffle (processing to return shuffled data to the original array)
Address signal rD and its error detection code IC
In addition to adding RC, error detection code DCRC and error correction code parity P and Q for detecting and correcting data transmission errors are added to form one synchronization block 5YNCB.
form.

A plurality of these synchronous blocks 5YNCB are put together to form one track block TB (FIG. 4(d)),
This track block TB is magnetically recorded on one track of the magnetic tape.

By the way, when playing back video signals recorded on magnetic tape, in addition to the normal playback mode that faithfully plays back the recorded video, there is usually a high-speed search mode that allows you to search the recorded video at high speed. be. In the normal playback mode, there is no problem because the recorded signals of each track of the magnetic tape are played back in order, but in the high-speed search mode, the playback head moves over a plurality of tracks T1 to T as shown in the trajectory HTR shown in FIG.
Since scanning is performed across N, it may not be possible to obtain all the data necessary for reproducing the video signal. Furthermore, even if the video data can be reproduced, if the address signal ID cannot be reproduced correctly, the synchronization block 5YNCB
It is not possible to re-create the video data of fr:i correctly.

Therefore, conventionally, in high-speed search mode, the address signal ID
The error detection code rcRc added to the address signal ID is used to detect errors in the reproduced address signal ID, and only if there is no error in the ID, the video data of the synchronization block 5YNCB is trusted and reconstructed, and the error is detected in the address signal ID. If there is, for example, a method has been used to replace it with the video data of the old synchronization block 5YNCB (that is, at the same screen position of the previous screen).

[Problem to be Solved by the Invention] However, in such a method, even if the video data is reproduced correctly, if there is an error in the address signal ID, all the video data of the synchronous block will not be used. It ends up being wasted. Further, in such a case, since the video data of the old synchronization block 5YNCB is replaced, there is a problem that the image quality deteriorates significantly.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a video signal reproducing device that can obtain images of good quality even in high-speed search mode.

[Means for Solving the Problems] A video playback device according to the present invention digitizes a video signal, adds identification data of the block to each block consisting of a predetermined number of video data, and records the video on a recording medium. A video reproducing device in a signal digital recording system, comprising a reproducing means for reproducing a recorded signal of the recording medium;
a data decoding means for decoding video data from a reproduction signal by the reproduction means; a memory means for storing the decoded video data; a write address counter for controlling the write address of the memory means; an error detection means for detecting an error; a dropout detection means for detecting the presence or absence of a dropout in the reproduced signal; and, when there is no error in the reproduced identification data, presetting the identification data at that time in the write address counter; The present invention is characterized by comprising logic means for incrementing the write address counter by a predetermined number of steps when there is an error in the identification data and dropout is not detected by the drop error detection means.

[Operation] With the above means, even if there is an identification data error in a synchronization block, as long as the video data is being reproduced, the video data is stored in the memory means and used for restoring the video. Therefore, compared to the conventional example in which old video data is simply used when there is an error in other identification data, the image quality is significantly improved.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. In addition, in this example, the aforementioned synchronization block 5YNCB is
Assume that they are arranged in order on one track. That is, it is assumed that the ID values are arranged in the order of 1, 23, . . . as shown in FIG.

In FIG. 1, the reproduction output of a reproduction head 10 is amplified by a reproduction amplifier 12, and the output of the reproduction amplifier 12 is supplied to a digital demodulation circuit 14 and a PLL circuit 16. PLL
The circuit 16 generates a clock synchronized with the reproduction signal, and the digital demodulation circuit 14 digitally demodulates the output of the reproduction amplifier 12 using this clock. Further, a dropout detection circuit 18 consisting of an envelope detector detects the presence or absence of a dropout from the output of the reproduction amplifier 12,
Outputs a troloughout signal when a dropout exists.

The data demodulated by the digital demodulation circuit 14 is EC
It is applied to the C decoder 20 and the ID decoder 22. E
The CC decoder 20 uses the error detection code DCRC and the error correction code parities P and Q to correct errors in the demodulated data and outputs the corrected data to the data bus 21, and the ID decoder 22
4? It outputs an i't ID signal 23 as well as an error check signal 24 from a built-in CRC checker. In addition, if there is no error in the ID signal, an error
The check signal 24 is '0°' and is 1'' if there is an error. The error check signal 24 is connected to the preset control terminal of the write address counter 26, and the address signal ID 23 is connected to the preset control terminal of the write address counter 26. Connect to the preset input terminal of the

If the error check signal 24 is "o", the address signal output 23 of the ID decoder 22 is preset to the write address counter 26. The value held by the write address counter 26 is applied to the address input of the memory 30 via the address hash 28 and, in response, the memory 3
0 reads data on the data bus 21 (output of the ECC decoder 20). At this time, the clock input of the write address counter 26 does not count up because the AND gate 32 is blocked by the error check signal 24.

Next, the error check signal 24 is '°1°' (error present), and the output of the dropout detection circuit 18 is ''''.
1″ (no dropout), PLL circuit 1
One clock per synchronous block generated by frequency divider 34 from the output of 6 passes through AND gate 32 and is applied to the clock input terminal of write address counter 26, and write address counter 26 counts by 1.・
Up.

Thereby, the memory 30 reads the output (decoded data) of the ECC decoder 20 into the next address.

During a high-speed search, when the magnetic head traces across the track boundary, the error check signal 24 is "1." and the output of the dropout detection circuit 18 is "'O."
゛ (with dropout). In this case, although not shown, writing to the memory 30 is prohibited. As a result, the data of the previous screen is saved in the memory 30.

Once one screen worth of data has been written to the memory 30 in the manner described above, the data will continue to be written. That is, the crystal oscillator 36
oscillates at a constant period, and the read address counter 38 counts up based on the output of the crystal oscillator 36. The output of read address counter 38 is connected to address bus 2.
8 is connected to the address of the memory 30,
As a result, the data stored in the memory 30 is sequentially read out to the data bus 21 and output from the output terminal 40.

As described above, even if an error occurs in the ID signal,
It is determined that it is simply a random error, and an ID value is set in the write address counter 26, so that the decoded data is read into the memory 30 and used effectively.

FIG. 2 shows a block diagram of another embodiment of the present invention.

The same components as in FIG. 1 are given the same reference numerals. Third
The figure shows the target recording format of FIG. 2, in which synchronization blocks 5yncb are interleaved between a plurality of tracks, and distributed within the same track at a predetermined number of offsets (10 in this example). This format was designed to prevent the noise bar from being fixed at the same position on the playback screen during high-speed search.

In FIG. 2, the write address counter consists of a first write address counter 42 that outputs the lower part of the write address and a write address counter 44 that outputs the higher part of the write address. Write address counter 4244 is, for example, a decimal counter, and the carry output of lower write address counter 42 is connected to the clock input of upper write address counter 44. The output of AND gate 32 is the write address.
It is connected to the clock manual control terminal of the counter 44.

Error check signal 24 of ID decoder 22 is 0''
(no error) and there is no dropout, the write address counter 42, 4.4 is preset with the value of the corresponding bit of the ID output 23 of the ID decoder 22, and the address signal from this is sent to the address bus 28. The signal is applied to the memory 30 via. Thereby, the memory 30 reads the decoded data output from the FCC decoder 20 and on the data bus 21.

Furthermore, when the error check signal 24 of the ID decoder 22 is "1" (error present) and the output of the dropout detection circuit 18 is "1" (no dropout), the output clock of the frequency divider 34 is applied to the clock input terminal of write address counter 44 via AND gate 32. This increments the address value defined by write address counters 42, 44 by ten.

That is, the memory 30 advances by an amount corresponding to the offset in the interleaving shown in FIG. 3, and the memory 30 reads the data on the data bus 21 into the corresponding storage location.

The other operations are the same as in the case of FIG. can be written,
Can be used for video playback.

In the above embodiment, the case where the synchronization blocks are arranged in a specific order on each track was explained as an example, but the present invention
It can be applied even if the arrangement and order are other than the above. Also, write address counters 26, 42.4
4 is not limited to the above-mentioned hardware configuration, but it goes without saying that a more general configuration may be used.

"Effects of the Invention As can be easily understood from the above explanation, according to the present invention, even if an error occurs in the block identification data, the video data of the block is used, so the image quality during high-speed search is improved. It can be significantly improved.

[Brief explanation of drawings]

Figure 1 is a block diagram of the configuration of an embodiment of the present invention, Figure 2 is a block diagram of the configuration of the second embodiment, Figure 3 is an explanatory diagram of the recording format targeted in Figure 2, and Figure 4 is a block diagram of the configuration of the second embodiment. FIG. 5 is an explanatory diagram of a video signal digital recording processing procedure, and FIG. 5 is an explanatory diagram of a head trace during high-speed search. 10: Playback head 12: Playback amplifier 16: PLL circuit 18 Nitrotube out detection circuit 20: ECC decoder 21: Data bus 22: ID decoder 23: ID signal 24: Error check signal 26
, 42, 44: Write address counter 28 Near address bus 30: Memory 32: AND gate 34
: Frequency divider

Claims (1)

[Claims] A video playback device in a video signal digital recording system that digitizes a video signal, adds identification data of the block to each block consisting of a predetermined number of video data, and records it on a recording medium, the video signal being recorded on the recording medium. a reproduction means for reproducing the video data, a data decoding means for decoding the video data from the reproduction signal by the reproduction means, a memory means for storing the decoded video data, and a write address counter for controlling the write address of the memory means. , an error detection means for detecting an error in the reproduced identification data, a dropout detection means for detecting the presence or absence of a dropout in the reproduced signal, and when there is no error in the reproduced identification data, writing the identification data at that time. The write address counter is preset in the address counter, and when there is an error in the identification data and a dropout is not detected by the dropout detection means, the write address counter is incremented by a predetermined number of steps. video playback device.