JPH0449313B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital video signal processing device, and more specifically to a digital video tape recorder (VTR) that records and reproduces color video signals in the form of digital signals.

Digitally encodes and records color video signals,
In a digital VTR for reproduction, the number of bits required for recording is enormous, so video information is distributed to multiple channels and recorded as multi-tracks using multiple rotating magnetic heads.
Figures 1a, b and c are recording patterns on a magnetic tape in a helical scan VTR, respectively.
An example of a configuration of a recording device and a configuration of a playback device is shown.
In this example, each field of the television video signal is recorded on two tracks. The channel division is, for example, screen division, in which the left half of the screen of the color video signal is recorded as channel A data on track a, and the right half of the screen is recorded as channel B data on track b.

On the other hand, during playback, the playback signals read out by heads 2-a and 2-b are decoded as channel A and channel B data by decoding circuit A and decoding circuit B, respectively, to obtain the original color video signal. . When the reproduction speed is equal to the recording speed (hereinafter referred to as normal), the head 2-a is controlled to always read track a, and the head 2-b is controlled to always read information from track b. On the other hand, the playback speed, such as low speed or high speed, is different from the recording speed. (hereinafter referred to as variable speed) When it comes to playback,
The heads 2-a and 2-b perform reading as shown by dotted lines in FIG. Therefore, during variable speed reproduction, in addition to the information on track a, information on track b is also read out from the head 2-a. Therefore, during variable speed playback, the head 2-a
If the signal read out is directly decoded by decoding circuit A, the signal that should originally be channel B information will be mistakenly processed as channel A information, so on the reproduced image, the signal originally on the right half of the screen will be There is a problem in that it is incorrectly displayed on the left half of the screen.

In order to solve this problem, a code for identifying the channel is added and recorded on each track, and during playback, the identification code is used to identify which channel the read data belongs to. Switching to the decoding circuit, a method is used in which channel A information is always decoded by decoding circuit A, and channel B information is always decoded by decoding circuit B. however,
This method of simply adding an identification code has no problem if channel identification is performed without error, but if a channel identification code error occurs due to, for example, dropouts caused by scratches on the tape, tape noise, equipment noise, etc. In some cases, channel identification is performed incorrectly. Alternatively, it may become impossible to identify the channel, resulting in a malfunction in channel switching control. In particular, during variable speed playback, reading is performed across multiple tracks, so phenomena such as a drop in the level of the playback signal occur between tracks, and more code errors occur than during normal playback. Therefore,
If an identification code is simply added, there is an extremely high possibility that channel switching control will be erroneous due to the influence of a code error, and there is a problem in that it is difficult to obtain a good reproduced image during variable speed reproduction.

SUMMARY OF THE INVENTION An object of the present invention is to realize a recording and reproducing apparatus which divides a digitalized video signal into a plurality of channels and performs correct reproduction even if a code error occurs during reproduction.

In order to achieve the above object, the present invention records identification codes such as channel identification, field identification, and block identification that are added at the time of recording with codes that have an error detection or error correction function. If a code error is detected in the code, or if error correction is impossible, the recording/reproducing device controls playback using an identification code predicted from an error-free or error-corrected identification code. It is composed of

That is, during reproduction, if no code error is detected in the identification code, it is determined that this identification code is correct, various controls are performed based on this identification code, and this identification code is stored.
When the next identification code arrives, the above operation is performed if there is no code error in the identification code. If there is a code error in the identification code, a predicted identification code is created based on the stored identification code, control is performed based on the predicted identification code, and the predicted identification code is stored. The same operation is repeated below.

The method for predicting the identification code differs depending on the nature of the identification code, but for example, in the case of channel identification, the previous value is retained, and for example, in the case of block number identification, the previous value plus 1 is used as predicted.

Additionally, an error detection code for error detection and correction,
An appropriate error correction code may be selected and used depending on the type of code error, and there are no particular restrictions.

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 2 shows the configuration of an embodiment of a digital video signal processing device according to the present invention, which is suitable for channel identification, field identification, etc. Further, the code structure on the recording medium in this embodiment will be explained next. Although FIG. 1a shows an example in which the digital signal is divided into two channels, if the digital signal is divided into three channels, the digital signal of each channel is recorded on each track. Furthermore, the digital signal of each channel on one track can be divided into multiple blocks.

Each block is composed of an identification code section and a data code section, and the identification code section is further composed of a channel identification code, a block identification code, and a field identification code. In this example, 3
This shows the case where different types of channel identification codes are used.
A 2-bit code is sufficient to identify 3 channels. For example, the A channel can be represented by 11, the B channel by 00, and the C channel by 10. However, in order to provide error detection capability, for example, the identification code of each channel is configured with the following code. Note that the upper two bits of each code correspond to the channels 11, 00, and 10 described above.

A channel 1100 B channel 0011 C channel 1010 Since the minimum distance of this code is 2, errors up to 1 bit within 4 bits are completely detectable.

The signals obtained from heads 2-a, 2-b, and 2-c are demodulated into binary codes by demodulators 3-a, 3-b, and 3-c, respectively. And demodulator 3-
The output codes of a, 3-b, and 3-c are input to selection circuits 4, 5, and 6, respectively. On the other hand, channel identification determination circuits 7, 8, and 9 identify channels based on channel identification codes. In this case, 1100
It is determined that 0011 is the A channel, 0011 is the B channel, and 1010 is the C channel, and this result is output. On the other hand, if the channel identification code is of a type other than the above three types, it is determined that there is a code error and an error flag is generated. When this flag exists, switches 10, 11, and 12 are activated by memory circuits 13 and 1, respectively.
4 and 15, that is, the predicted identification result,
If this flag is not present, the outputs of the channel identification determination circuits 7, 8, and 9 are selected. Memory circuit 13,1
Reference numerals 4 and 15 output the channel state immediately before the input, and in this configuration, prediction is, for example, holding the previous value. For example, a signal read out by the head 2-a is demodulated by the demodulator 3-a, and the second
It is determined that the channels are A, B, C, and A as shown in Figure b. As for the determination result of the identification code shown in the figure, if there is no code error, the corresponding channel identification result is obtained, but if there is a code error, an error flag is generated. Therefore, if there is a code error,
The predicted identification code, which is the output of the memory circuit and which holds the previous value, is selected, and a control signal as shown in the figure is obtained. These control signals are input to the control circuit 16, the output of the selection circuit 4 is always the A channel signal, the output of the selection circuit 5 is always the B channel signal,
A signal for controlling the selection circuit so that the output of the selection circuit 6 always becomes a C channel signal is output.

Therefore, the outputs of the selection circuits 4, 5, and 6 are respectively connected to the decoding circuit of the corresponding channel.

That is, even if an error occurs in the channel identification code, in this case, channel switching can be controlled without malfunction using a prediction signal using the previous identification results.

FIG. 3 shows another embodiment of the digital video signal processing apparatus according to the present invention. In this embodiment, when there is an error in the identification code, a prediction signal is created by adding a constant value to the result obtained from the previous identification code, and this is used to calculate the effect of the code error in the identification code. This prevents malfunctions due to This embodiment is suitable for a block identification code assigned to a block having a fixed number of bits, for example, about 1000 bits.

In digital VTRs and the like, in order to remove jitter that occurs during playback, the jitter is removed by writing the reproduced data into memory and reading out the jitter-free read clock memory. Writing and reading from this memory is performed in block units. That is, the memory write address and read address are controlled based on the information identified by the block identification code. Therefore, if the block identification code does not have a function such as error detection, an error in the block identification code during memory writing will cause malfunction, but the method according to the present invention cannot completely eliminate the effects of code errors. It is possible.

In FIG. 3a, the block identification judgment circuit 17
detects whether or not there is a code error in the block identification code, and outputs the corresponding block information if there is no code error. If a code error is included, an error flag is output. This error flag controls the switch 18, which selects the prediction circuit 19 if there is an error, and selects the block identification judgment circuit 17 if there is no error. The obtained control signal is then applied to the write address generation circuit 20, and data is written into the memory circuit 22 from the address position corresponding to the block. On the other hand, the prediction circuit 19 outputs a result obtained by adding, for example, 1 to the control signal. Now, suppose that an error occurs in the block identification code as shown in FIG. 3b. Now 11
If an error is detected in the th block, it is replaced with the predicted signal 11 predicted from the block 10 immediately before the error in the control signal. Further, for code errors at positions 15 and 16, predicted values of 15 and 16 of the predicted signal are taken. Therefore, the control signal yields the same result as when there is no code error in the block identification code. On the other hand, since reading is performed from the read address generation circuit 21 in a fixed procedure, jitter can be removed without malfunction.

As described above, according to the present invention, even if a code error occurs in the identification code, it is possible to perform stable reproduction control operations without malfunctions due to the code error.

It should be noted that when an error correction code is added to an identification code, it is clear that the operation when a code error is detected as described in the main text should be performed when the code error cannot be corrected.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a general digital video signal processing device, and FIGS. 2 and 3 are diagrams showing the configuration of an embodiment of the digital video signal processing device according to the present invention. 3-a, 3-b, 3-c... demodulator, 4, 5,
6... Selection circuit, 7, 8, 9... Channel identification judgment circuit, 13, 14, 15... Memory circuit, 16...
...Control circuit, 17...Block identification judgment circuit, 1
9... Prediction circuit, 20... Write address generation circuit, 21... Read address generation circuit, 22
...Memory circuit, 10, 11, 12, 18...Switch.

Claims (1)

[Claims] 1. In a digital video signal processing device that divides a digital signal converted from a video signal into a plurality of channels and records and reproduces the digital signal, the recording section includes a digital signal converted into a plurality of channels. , a means for recording on a recording medium an identification code that is an error-detectable code and includes at least a code for identifying the channel of each digital signal, and the reproducing unit reads out an identification code from the recording medium. a detection means for detecting an error in an identification code, a prediction signal generation means for predicting and retaining an identification code at a next time from an identification code at a certain time and outputting it as a prediction signal; When a code error in the issued identification code is detected, the predicted signal is selected as the identification code instead of the identification code in which the code error was detected, and the digital signal is transmitted using the channel identified by the predicted signal. 1. A digital video signal processing device comprising: means for controlling reproduction of a digital video signal. 2. The recording means of the recording section further includes a block identification code for identifying a block of the digital signal in the identification code, and the prediction signal generating means of the reproduction section further includes a block identification code included in the identification code at a certain point in time. 2. A digital video signal processing apparatus according to claim 1, further comprising means for setting a value obtained by adding a predetermined value to a block identification code as the next block identification code.