JPH06284160A - Method and device for detecting synchronizing block - Google Patents

Abstract

PURPOSE:To provide a method and device for detecting synchronizing block which can properly detect a synchronizing block by preventing the influence of the detection omission or erroneous detection of a synchronizing code and can properly detect the synchronizing block even after data get discontinuous. CONSTITUTION:This device is provided with an RS flip-flop 15 for detecting first and second states and constituted so as to start the second state when two continuous synchronizing codes are detected separately for one synchronizing block term in an input data row at the time of the first state or to start the first state when two continuous synchronizing codes separated for one synchronizing block term can not be detected at the time of the second state, and a synchronizing signal showing the synchronizing block position of a data row, for which the input data row is delayed for one synchronizing block term, is outputted in the cycle of one synchronizing block term from the time point when the first state is changed into the second state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous block detecting method and a synchronous block detecting device for detecting a synchronous block having a predetermined period included in digital information such as a digital audio tape recorder or a digital VTR. .

[0002]

2. Description of the Related Art In recent years, digital audio tape recorders and digital VTRs have been developed which digitize audio signals and video signals and record them without deterioration. FIG. 7 shows an example of a reproduction data sequence of a digital VTR.

In FIG. 7, reference numerals 1a to 1d denote synchronization blocks having a predetermined number of bits, and a synchronization code 2 is inserted at the beginning of each synchronization block. The portions other than the synchronization code 2 of the synchronization blocks 1a to 1d include video or audio data and error correction code.
In order to correctly reproduce the video or audio from the reproduction data series, it is necessary to correctly detect the boundaries of the sync blocks.

Therefore, in order to prevent the influence of the omission of detection of the synchronization code due to a code error and the false detection of erroneously detecting the portion other than the synchronization code as the synchronization code, synchronization is protected. Generally, for the protection of synchronization, a synchronization protection circuit including a competition counter including a counter that counts synchronization coincidence pulses and a counter that counts synchronization disagreement pulses is used (for example, Japanese Patent Publication No. 4-67819).

[0005]

By the way, in the VTR, there are cases in which reproduction is performed across recording tracks in search reproduction and the like, at which time the data series becomes discontinuous. Figure 8
Shows an example of the data series in this case. In FIG.
Reference numerals 3a to 3d are sync blocks of the same track, and at position 5, reproduction data from another track is switched to, and reference numerals 4a to 4d are sync blocks of the track. With respect to such a reproduced data sequence, the conventional sync protection circuit protects against omission of detection of a sync code due to a code error and erroneous detection in which a portion other than the sync code is erroneously detected as a sync code. It takes time until a sync block is correctly detected after the continuous track switching position 5, and some sync blocks after the track switching cannot be correctly detected. For this reason, there is a problem that the data in this portion cannot be reproduced correctly and the reproduced image quality is deteriorated at the time of searching.

[0006] Therefore, the present invention is to solve the above problems.
Synchronous blocks are correctly detected by preventing the influence of omission of detection of synchronous code due to code error and erroneous detection of parts other than synchronous code as synchronous code, and synchronization is performed immediately after data becomes discontinuous. An object of the present invention is to provide a synchronous block detecting method and a synchronous block detecting device which can detect a block without fail and can ensure excellent reproduction image quality during search reproduction when used in a VTR.

[0007]

In order to achieve the above-mentioned object, the synchronous block detecting method of the present invention comprises first and second methods.
Has a state of 1 and has 1 in the input data string in the first state.
When two consecutive sync codes are detected with a separation of a sync block period, the second state is entered, and 1 is entered in the second state.
It is configured to shift to a first state when two consecutive sync codes separated by a sync block period cannot be detected, and a sync signal indicating a sync block position of a data string delayed by one sync block period from the input data string The signal is output in one synchronization block period cycle from the time when the state 1 shifts to the second state.

Further, the synchronous block detecting device of the present invention is
Data delay means for delaying the input data string by one sync block period, sync code detecting means for detecting a sync code from the input data string and outputting a sync code detection signal, and delaying the sync code detection signal by one sync block period. Detection signal delay means, state holding means for indicating the first and second states, and counter means for outputting a synchronization signal in one synchronization block period cycle, and the synchronization code detection is performed in the first state. When both the signal and the output of the detection signal delay means indicate that a sync code has been detected, the state shifts to the second state and the counter means is reset, and in the second state the synchronization signal When the sync code detection signal indicates that the sync code has not been detected at the time when
The output data of the data delay means and the sync signal indicating the position of the sync block are output.

[0009]

According to the present invention, with the above configuration, when the first state is shifted to the second state, the sync block is detected from the sync code at the head of the sync block and the sync code at the head of the subsequent sync block. And otherwise,
The cycle is maintained until the state shifts to the first state and the state shifts to the second state again due to the loss of the sync code. by this,
It is possible to prevent the influence of the omission of detection of the synchronization code due to a code error and the false detection of erroneously detecting the portion other than the synchronization code as the synchronization code. Also, since one sync code omission causes the transition to the first state, two sync codes before and after the sync block are detected, and the transition to a new sync state (second state) occurs, the sync block remains even immediately after the track switching. It can be detected correctly without overlooking.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the sync block detecting apparatus of the present invention using the sync block detecting method of the present invention will be described below. FIG. 1 is a block diagram of the first embodiment.

In FIG. 1, an input data string 17 is input to a delay circuit 10 which delays a signal for one sync block period, and a delayed signal 22 is output. The input data string 17 is also input to the sync code detection circuit 11. The sync code detection circuit 11 evaluates the degree of coincidence with a predetermined sync code, and outputs a signal at H level if it is recognized as a sync code, and at L level otherwise, as the signal 18. The delay circuit 12 delays the signal 18 by one synchronization block period and outputs it as a signal 19.

The RS flip-flop 15 outputs a signal 20 indicating which one of the two states is present. When the signal 20 is at the L level, it indicates the first state and is at the H level. Sometimes it indicates the second state. The RS flip-flop 15 is a gate circuit 1
3 output signal. That is, in the first state (the signal 20 is at the L level), when the two consecutive synchronization codes are detected at a distance of one synchronization block period (when the signals 18 and 19 are both at the H level), the second state is detected. The state changes (the signal 20 is at the H level). Also at this time,
The counter 16 that outputs the synchronization signal 21 in the cycle of one synchronization block period is simultaneously reset.

The RS flip-flop 15 is reset by the output signal of the gate circuit 14. That is, in the second state (the signal 20 is at the H level), when two consecutive sync codes separated by one sync block period cannot be detected, that is, when the sync signal 21 is at the H level and the signal 18 is at the L level. Transition to the first state.

Next, a more specific operation of the above-described first embodiment will be described with reference to the timing chart.

FIG. 2 is a timing chart showing an example of changes in the signals 17-18. In this example, the input signal 17
Contains synchronization codes 25a to 25f. In the portion 26 where the synchronization code should originally exist, the synchronization code detection circuit 11 cannot detect the synchronization code due to a code error. At this time, a signal indicating a state from time t _{1 at} which two consecutive sync codes separated by one sync block period cannot be detected until time t _{2 at} which two consecutive sync codes separated by one sync block period are detected again. 20 becomes L level, and becomes the first state. However, the counter 16
Continues to output the sync signal 21 in a cycle of one sync block period without being reset during this period. Therefore, even if the sync signal is lost due to a code error, the sync block can be correctly detected for the signal 22.

FIG. 3 is a timing chart showing another example of changes in the signals 17-18. In this example, input signal 1
7 includes synchronization codes 27a to 27g. Also,
It is assumed that the portions 28a and 28b without the original synchronization code happen to have the same code string as the synchronization code, and 28a and 28b are separated by one synchronization block period. In this case, the signal 20 indicating the state is always at the H level (second state)
It is in. Therefore, even if the same code sequence as the continuous sync code happens to be separated by one sync block period, the sync signal 21 to be output is not affected by these, and the sync block is detected correctly for the signal 22. can do.

FIG. 4 is a timing chart showing another example of changes in the signals 17 to 18, which is an example in which the data sequence becomes discontinuous as in the case of VTR search reproduction. In this example, the input signal 17 includes a synchronization code 29 a to 29 c, the data sequence becomes discontinuous at the time t _4, then, contains synchronization code 30a~30d new sequence. In this case, the signal 20 indicating the state shifts to the L level (first state) at time t ₅ , and then
First, at time t ₆ when two consecutive synchronization codes are detected, the second state is entered and the counter 16 is reset. Therefore, the synchronization signal 21 is the input signal 1
With respect to the signal 22 obtained by delaying 7 by 1 sync block, a correct sync block can be detected immediately after the discontinuity of the signal.

As is clear from the above description, in the present embodiment, the effects of omission of detection of the synchronization code due to a code error and erroneous detection of a portion other than the synchronization code as the synchronization code are prevented, and the VTR is Even when the data sequence becomes discontinuous as in the case of the search reproduction described above, the synchronization block can be correctly detected without missing the synchronization block immediately after that.

Next, a second embodiment of the synchronous block detecting apparatus of the present invention using the synchronous block detecting method of the present invention will be described. FIG. 5 is a block diagram showing the second embodiment. The same numbers are assigned to blocks having the same functions as those in the first embodiment.

The present embodiment is different from the first embodiment in that the operation is controlled by providing a third state in addition to the first and second states. That is, in the present embodiment, the RS flip-flop 40 set by the output signal of the delay circuit 46 that delays the system reset signal 45 for one synchronization block period is provided, and the third state is set when the signal 44 is at the H level. Indicates that. Further, the RS flip-flop 15 is reset by the gate circuit 43 which takes the logical sum of the output of the gate circuit 14 and the system reset signal. Further, the counter 16 is configured to be reset by the output of the gate circuit 42 which takes the logical sum of the output of the gate circuit 13 and the output of the signal 19 via the gate circuit 41.

In this embodiment, the system reset signal 45 is input when it is clear that the signal of the input data series 17 is discontinuous, such as when the VTR is switched to the reproduction of another track. The system reset signal 45 can be created by detecting the reproduction signal amplitude.

FIG. 6 is a timing chart showing an example of changes in the signals 17 to 18, the signal 45, and the signal 44 for explaining the specific operation of this embodiment. In this example, the input signal 17 includes the synchronization codes 50a to 50c, and the data sequence becomes discontinuous at time t ₁ ,
After that, the new series of synchronization codes 51a to 51c are included. Further, in the portion 52 which originally has a sync code, the sync code cannot be detected by the sync code detection circuit 11 due to a code error. In this case, the system reset signal is issued at time t ₁ and the signal 44 changes to show the state 3 with a delay of one synchronization block period.

After that, the counter 16 is reset at the time t ₂ when the signal 19 first becomes H level. As a result, a signal 22 obtained by delaying the input signal 17 by one synchronization block is generated.
On the other hand, the correct synchronization block can be detected immediately after the discontinuity of the signal. In particular, the present embodiment is characterized in that even if the second sync code after the discontinuity of the input data string cannot be detected, the correct sync block can be detected immediately after the discontinuity of the signal.

[0024]

As described above, according to the present invention, a sync block is correctly detected by preventing the omission of detection of a sync code due to a code error and the erroneous detection of a portion other than the sync code being mistakenly detected as a sync code. At the same time, the synchronization block can be detected without missing the synchronization block immediately after the signal becomes discontinuous. Therefore, when the present invention is applied to a VTR, excellent reproduction image quality can be secured even during search reproduction.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the first embodiment.

FIG. 3 is a timing chart illustrating the operation of the first embodiment.

FIG. 4 is a timing diagram illustrating the operation of the first embodiment.

FIG. 5 is a configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the second embodiment.

FIG. 7 is a signal diagram illustrating a reproduction data string of a digital VTR.

FIG. 8 is a signal diagram illustrating a reproduction data string of a digital VTR.

[Explanation of symbols]

 10 delay circuit 11 synchronous code detection circuit 12 delay circuit 15, 40 RS flip-flop 16 counter

Claims (4)

[Claims] 1. Having a first state and a second state, and in the first state, two synchronization block periods are separated from each other in the input data string.
When two consecutive sync codes are detected, the state shifts to the second state, and in the second state, one synchronization block period
When two consecutive sync codes cannot be detected, a transition is made to the first state, and a sync signal indicating the sync block position of the data string obtained by delaying the input data string by one sync block period is sent from the first state to the second state. 1 from the time of transition to
A synchronous block detection method that outputs in a synchronous block period cycle. 2. A data delay means for delaying an input data string by one sync block period, a sync code detecting means for detecting a sync code from the input data string and outputting a sync code detection signal, and the sync code detection signal. In the first state, the detection signal delay means delays by one synchronization block period, the state holding means indicating the first and second states, and the counter means which outputs the synchronization signal in one synchronization block period cycle are provided. When the synchronous code detection signal and the output of the detection signal delay means both indicate that the synchronous code is detected,
And the counter means is reset, and when the synchronous code detection signal indicates that the synchronous code is not detected at the time when the synchronous signal is output in the second state, the state shifts to the second state. And a sync block detecting device for outputting the output data of the data delay means and the sync signal indicating the position of the sync block. 3. A first state, a second state, and a third state. When the synchronization code is detected in the input data string in the third state, the state shifts to the first state. Occasionally, when two consecutive synchronization codes are detected in the input data sequence with a separation of one synchronization block period, the second state is entered, and in the second state, two consecutive synchronization blocks are separated by one synchronization block period. When the sync code cannot be detected, the first state is entered, and when the first or second state is entered, the predetermined system reset signal is entered into the third state, and the input data string is delayed by one sync block period. A synchronization signal that outputs a synchronization signal indicating the synchronization block position of the data sequence in one synchronization block period cycle from the time of transition from the first state to the second state or the transition from the third state to the first state. Block detection method. 4. A data delay means for delaying an input data string by one sync block period, a sync code detecting means for detecting a sync code from the input data string and outputting a sync code detection signal, and the sync code detection signal. The detection signal delay means for delaying one synchronization block period, the state holding means for indicating the first, second and third states, and the counter means for outputting the synchronization signal in one synchronization block period cycle are provided. When the detection signal indicates that the synchronization code is detected in the state of 1), the state transitions to the first state, and in the first state, the synchronization code detection signal and the output of the detection signal delay means are When both indicate that a sync code has been detected, the second
To the first state when the sync code detection signal indicates that no sync code is detected at the time when the sync signal is output in the second state. When transitioning from the second state to the third state by a predetermined system reset signal, transitioning from the first state to the second state, and transitioning from the third state to the first state A synchronous block detection device configured to reset the counter means when outputting, and output the output data of the data delay means and the synchronous signal indicating the position of the synchronous block.